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CD4520BPWR
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Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4520BPWR++**Texas Instruments** · Counters, Dividers · TSSOP-16++CD4520BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLOCK A | input | Counter A clock input that increments the counter on a positive-going transition when ENABLE A is high; input range is -0.5 V to VDD+0.5 V. |+| 2 | ENABLE A | input | Counter A enable input that increments the counter on a negative-going transition when CLOCK A is low, and is held high for single-unit operation on the clock's positive edge. |+| 3 | Q1A | output | Counter A stage 1 (Q1) output, cleared to 0 by a high level on RESET A. |+| 4 | Q2A | output | Counter A stage 2 (Q2) output, cleared to 0 by a high level on RESET A. |+| 5 | Q3A | output | Counter A stage 3 (Q3) output, cleared to 0 by a high level on RESET A. |+| 6 | Q4A | output | Counter A stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET A. |+| 7 | RESET A | input | Counter A reset input; a high level clears Q1 through Q4 to 0. |+| 8 | VSS | power_in | Ground (negative supply) terminal, the reference for the -0.5 V to +20 V VDD absolute-maximum rating. |+| 9 | CLOCK B | input | Counter B clock input that increments the counter on a positive-going transition when ENABLE B is high; input range is -0.5 V to VDD+0.5 V. |+| 10 | ENABLE B | input | Counter B enable input that increments the counter on a negative-going transition when CLOCK B is low, and is held high for single-unit operation on the clock's positive edge. |+| 11 | Q1B | output | Counter B stage 1 (Q1) output, cleared to 0 by a high level on RESET B. |+| 12 | Q2B | output | Counter B stage 2 (Q2) output, cleared to 0 by a high level on RESET B. |+| 13 | Q3B | output | Counter B stage 3 (Q3) output, cleared to 0 by a high level on RESET B. |+| 14 | Q4B | output | Counter B stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET B. |+| 15 | RESET B | input | Counter B reset input; a high level clears Q1 through Q4 to 0. |+| 16 | VDD | power_in | Positive supply, recommended 3 V to 18 V over the full package temperature range, with an absolute maximum of -0.5 V to +20 V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4520BPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4520bpwr-etched.step` / `cd4520bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4520bpwr.step` / `cd4520bpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4520b.pdf) (21 pp, sha256 `c28162391ada6d6a`, retrieved 2026-10-03, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4520bpwr-datasheet.pdf)
page.jsonadded+208@@ -0,0 +1,208 @@+{+ "slug": "cd4520bpwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4520bpwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4520bpwr.kicad_sym",+ "cd4520bpwr.kicad_mod",+ "cd4520bpwr.glb",+ "cd4520bpwr.step",+ "cd4520bpwr.lbr",+ "docs/hero.png",+ "docs/cd4520bpwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd4520bpwr-hero.glb",+ "cd4520bpwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD4520BPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4520b.pdf",+ "parts": {+ "symbol": "cd4520bpwr.kicad_sym",+ "footprint": "cd4520bpwr.kicad_mod",+ "model_3d": "cd4520bpwr-hero.glb",+ "model_3d_plain": "cd4520bpwr.glb",+ "model_3d_step": "cd4520bpwr-etched.step",+ "model_3d_step_plain": "cd4520bpwr.step",+ "lbr": "cd4520bpwr.lbr"+ },+ "distributor_links": {+ "lcsc": 2870326,+ "digikey": "296-31532-2-ND",+ "mouser": "595-CD4520BPWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T07:49:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-31532-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CD4520BPWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLOCK A",+ "type": "input",+ "description": "Counter A clock input that increments the counter on a positive-going transition when ENABLE A is high; input range is -0.5 V to VDD+0.5 V."+ },+ {+ "number": "2",+ "name": "ENABLE A",+ "type": "input",+ "description": "Counter A enable input that increments the counter on a negative-going transition when CLOCK A is low, and is held high for single-unit operation on the clock's positive edge."+ },+ {+ "number": "3",+ "name": "Q1A",+ "type": "output",+ "description": "Counter A stage 1 (Q1) output, cleared to 0 by a high level on RESET A."+ },+ {+ "number": "4",+ "name": "Q2A",+ "type": "output",+ "description": "Counter A stage 2 (Q2) output, cleared to 0 by a high level on RESET A."+ },+ {+ "number": "5",+ "name": "Q3A",+ "type": "output",+ "description": "Counter A stage 3 (Q3) output, cleared to 0 by a high level on RESET A."+ },+ {+ "number": "6",+ "name": "Q4A",+ "type": "output",+ "description": "Counter A stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET A."+ },+ {+ "number": "7",+ "name": "RESET A",+ "type": "input",+ "description": "Counter A reset input; a high level clears Q1 through Q4 to 0."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground (negative supply) terminal, the reference for the -0.5 V to +20 V VDD absolute-maximum rating."+ },+ {+ "number": "9",+ "name": "CLOCK B",+ "type": "input",+ "description": "Counter B clock input that increments the counter on a positive-going transition when ENABLE B is high; input range is -0.5 V to VDD+0.5 V."+ },+ {+ "number": "10",+ "name": "ENABLE B",+ "type": "input",+ "description": "Counter B enable input that increments the counter on a negative-going transition when CLOCK B is low, and is held high for single-unit operation on the clock's positive edge."+ },+ {+ "number": "11",+ "name": "Q1B",+ "type": "output",+ "description": "Counter B stage 1 (Q1) output, cleared to 0 by a high level on RESET B."+ },+ {+ "number": "12",+ "name": "Q2B",+ "type": "output",+ "description": "Counter B stage 2 (Q2) output, cleared to 0 by a high level on RESET B."+ },+ {+ "number": "13",+ "name": "Q3B",+ "type": "output",+ "description": "Counter B stage 3 (Q3) output, cleared to 0 by a high level on RESET B."+ },+ {+ "number": "14",+ "name": "Q4B",+ "type": "output",+ "description": "Counter B stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET B."+ },+ {+ "number": "15",+ "name": "RESET B",+ "type": "input",+ "description": "Counter B reset input; a high level clears Q1 through Q4 to 0."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply, recommended 3 V to 18 V over the full package temperature range, with an absolute maximum of -0.5 V to +20 V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives one 16-lead terminal assignment (top view) shared by all package types. I did no",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 12,+ "cost_usd": 0.1435,+ "at": "2026-10-03T07:48:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4520b.pdf",+ "pages": 21,+ "sha256": "c28162391ada6d6a",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}