component
CD4520BPWR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4520BPWR
Texas Instruments · Counters, Dividers · TSSOP-16
CD4520BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK A | input | Counter A clock input that increments the counter on a positive-going transition when ENABLE A is high; input range is -0.5 V to VDD+0.5 V. |
| 2 | ENABLE A | input | Counter A enable input that increments the counter on a negative-going transition when CLOCK A is low, and is held high for single-unit operation on the clock's positive edge. |
| 3 | Q1A | output | Counter A stage 1 (Q1) output, cleared to 0 by a high level on RESET A. |
| 4 | Q2A | output | Counter A stage 2 (Q2) output, cleared to 0 by a high level on RESET A. |
| 5 | Q3A | output | Counter A stage 3 (Q3) output, cleared to 0 by a high level on RESET A. |
| 6 | Q4A | output | Counter A stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET A. |
| 7 | RESET A | input | Counter A reset input; a high level clears Q1 through Q4 to 0. |
| 8 | VSS | power_in | Ground (negative supply) terminal, the reference for the -0.5 V to +20 V VDD absolute-maximum rating. |
| 9 | CLOCK B | input | Counter B clock input that increments the counter on a positive-going transition when ENABLE B is high; input range is -0.5 V to VDD+0.5 V. |
| 10 | ENABLE B | input | Counter B enable input that increments the counter on a negative-going transition when CLOCK B is low, and is held high for single-unit operation on the clock's positive edge. |
| 11 | Q1B | output | Counter B stage 1 (Q1) output, cleared to 0 by a high level on RESET B. |
| 12 | Q2B | output | Counter B stage 2 (Q2) output, cleared to 0 by a high level on RESET B. |
| 13 | Q3B | output | Counter B stage 3 (Q3) output, cleared to 0 by a high level on RESET B. |
| 14 | Q4B | output | Counter B stage 4 (Q4) output, which can be connected to the ENABLE input of the next counter for ripple cascading and is cleared by a high level on RESET B. |
| 15 | RESET B | input | Counter B reset input; a high level clears Q1 through Q4 to 0. |
| 16 | VDD | power_in | Positive supply, recommended 3 V to 18 V over the full package temperature range, with an absolute maximum of -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4520BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4520bpwr-etched.step/cd4520bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4520bpwr.step/cd4520bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
c28162391ada6d6a, retrieved 2026-10-03, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).