component
CD4520BM
Public Made by Adomby adom
lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4520BM
lingxingic · Counters, Dividers · SOP-16
CD4520BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP0_1 | input | Clock input for counter 1 that advances the counter on a LOW-to-HIGH transition when nCP1 is LOW and nMR is LOW, per the function table. |
| 2 | CP1_1 | input | Clock input for counter 1 that advances the counter on a HIGH-to-LOW transition when nCP0 is HIGH and nMR is LOW, per the function table. |
| 3 | Q0_1 | output | Counter 1 binary output bit 0, forced LOW while master reset MR_1 is HIGH. |
| 4 | Q1_1 | output | Counter 1 binary output bit 1, forced LOW while master reset MR_1 is HIGH. |
| 5 | Q2_1 | output | Counter 1 binary output bit 2, forced LOW while master reset MR_1 is HIGH. |
| 6 | Q3_1 | output | Counter 1 binary output bit 3, forced LOW while master reset MR_1 is HIGH. |
| 7 | MR_1 | input | Master reset input for counter 1; when HIGH, outputs Q0 to Q3 are forced LOW regardless of the clock inputs. |
| 8 | VSS | power_in | Ground supply voltage, the 0 V reference for all voltages in the datasheet. |
| 9 | CP0_2 | input | Clock input for counter 2 that advances the counter on a LOW-to-HIGH transition when nCP1 is LOW and nMR is LOW, per the function table. |
| 10 | CP1_2 | input | Clock input for counter 2 that advances the counter on a HIGH-to-LOW transition when nCP0 is HIGH and nMR is LOW, per the function table. |
| 11 | Q0_2 | output | Counter 2 binary output bit 0, forced LOW while master reset MR_2 is HIGH. |
| 12 | Q1_2 | output | Counter 2 binary output bit 1, forced LOW while master reset MR_2 is HIGH. |
| 13 | Q2_2 | output | Counter 2 binary output bit 2, forced LOW while master reset MR_2 is HIGH. |
| 14 | Q3_2 | output | Counter 2 binary output bit 3, forced LOW while master reset MR_2 is HIGH. |
| 15 | MR_2 | input | Master reset input for counter 2; when HIGH, outputs Q0 to Q3 are forced LOW regardless of the clock inputs. |
| 16 | VDD | power_in | Supply voltage, recommended range 3 V to 15 V referenced to VSS, with an absolute maximum of +18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VDD | -0.5 | 18 | V | Voltages referenced to VSS | 5 | |
| input voltage | VI | -0.5 | V | all inputs; printed max is VDD+0.5 (not numeric) | 5 | ||
| DC input current | IIK | -10 | 10 | mA | any one input | 5 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| soldering temperature | TL | 260 | ℃ | 10s, SOP/TSSOP | 5 | ||
| supply voltage | VDD | 3 | 15 | V | 5 | ||
| ambient temperature | Tamb | -40 | 125 | ℃ | in free air | 5 | |
| HIGH-level input voltage | VIH | 3.5 | V | Tamb=-40℃ to +125℃; VDD=5V | 7 | ||
| HIGH-level input voltage | VIH | 7 | V | Tamb=-40℃ to +125℃; VDD=10V | 7 | ||
| HIGH-level input voltage | VIH | 11 | V | Tamb=-40℃ to +125℃; VDD=15V | 7 | ||
| LOW-level input voltage | VIL | 1.5 | V | Tamb=-40℃ to +125℃; VDD=5V | 7 | ||
| LOW-level input voltage | VIL | 3 | V | Tamb=-40℃ to +125℃; VDD=10V | 7 | ||
| LOW-level input voltage | VIL | 4 | V | Tamb=-40℃ to +125℃; VDD=15V | 7 | ||
| HIGH-level output voltage | VOH | 4.95 | V | Tamb=-40℃ to +125℃; VDD=5V; /IO/<1uA | 7 | ||
| HIGH-level output voltage | VOH | 9.95 | V | Tamb=-40℃ to +125℃; VDD=10V; /IO/<1uA | 7 | ||
| HIGH-level output voltage | VOH | 14.95 | V | Tamb=-40℃ to +125℃; VDD=15V; /IO/<1uA | 7 | ||
| LOW-level output voltage | VOL | 0.05 | V | Tamb=-40℃ to +125℃; VDD=5V; /IO/<1uA | 7 | ||
| HIGH-level output current | IOH | -0.3 | mA | Tamb=-40℃ to +125℃; VDD=5V; VO=4.6V | 7 | ||
| HIGH-level output current | IOH | -1.15 | mA | Tamb=-40℃ to +125℃; VDD=5V; VO=2.5V | 7 | ||
| HIGH-level output current | IOH | -0.45 | mA | Tamb=-40℃ to +125℃; VDD=10V; VO=9.5V | 7 | ||
| HIGH-level output current | IOH | -1.4 | mA | Tamb=-40℃ to +125℃; VDD=15V; VO=13.5V | 7 | ||
| LOW-level output current | IOL | 0.29 | mA | Tamb=-40℃ to +125℃; VDD=5V; VO=0.4V | 7 | ||
| LOW-level output current | IOL | 0.38 | mA | Tamb=-40℃ to +125℃; VDD=10V; VO=0.5V | 7 | ||
| LOW-level output current | IOL | 1.2 | mA | Tamb=-40℃ to +125℃; VDD=15V; VO=1.5V | 7 | ||
| input leakage current | II | -4 | 4 | uA | Tamb=-40℃ to +125℃; VDD=15V; VI=15V or GND | 7 | |
| supply current | IDD | 7.5 | uA | Tamb=-40℃ to +125℃; VDD=5V; VI=5V or GND; IO=0A | 7 | ||
| supply current | IDD | 15 | uA | Tamb=-40℃ to +125℃; VDD=10V; VI=10V or GND; IO=0A | 7 | ||
| supply current | IDD | 30 | uA | Tamb=-40℃ to +125℃; VDD=15V; VI=15V or GND; IO=0A | 7 | ||
| HIGH to LOW propagation delay time (nCP0, nCP1 to nQn) | tPHL | 265 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; see Figure 4 | 9 | ||
| HIGH to LOW propagation delay time (nCP0, nCP1 to nQn) | tPHL | 120 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; see Figure 4 | 9 | ||
| HIGH to LOW propagation delay time (nCP0, nCP1 to nQn) | tPHL | 95 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; see Figure 4 | 9 | ||
| HIGH to LOW propagation delay time (nMR to nQn) | tPHL | 180 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; see Figure 4 | 9 | ||
| HIGH to LOW propagation delay time (nMR to nQn) | tPHL | 85 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; see Figure 4 | 9 | ||
| HIGH to LOW propagation delay time (nMR to nQn) | tPHL | 60 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; see Figure 4 | 9 | ||
| LOW to HIGH propagation delay time (nCP0, nCP1 to nQn) | tPLH | 265 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; see Figure 4 | 9 | ||
| LOW to HIGH propagation delay time (nCP0, nCP1 to nQn) | tPLH | 120 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; see Figure 4 | 9 | ||
| LOW to HIGH propagation delay time (nCP0, nCP1 to nQn) | tPLH | 95 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; see Figure 4 | 9 | ||
| transition time (nQn) | tTHL, tTLH | 145 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; see Figure 4 | 9 | ||
| transition time (nQn) | tTHL, tTLH | 72 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; see Figure 4 | 9 | ||
| transition time (nQn) | tTHL, tTLH | 48 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; see Figure 4 | 9 | ||
| pulse width (nCP0 input LOW, first block) | tw | 72 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| pulse width (nCP0 input LOW, first block) | tw | 36 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| pulse width (nCP0 input LOW, first block) | tw | 24 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| pulse width (nCP0 input LOW, third block) | tw | 36 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| pulse width (nCP0 input LOW, third block) | tw | 24 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| pulse width (nCP0 input LOW, third block) | tw | 20 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; nCP0 input LOW; minimum width; see Figure 5 | 9 | ||
| recovery time (nMR input) | trec | 60 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; see Figure 5 | 9 | ||
| recovery time (nMR input) | trec | 36 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; see Figure 5 | 9 | ||
| recovery time (nMR input) | trec | 24 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; see Figure 5 | 9 | ||
| set-up time (nCP0 to nCP1) | tsu | 60 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; nCP0 to nCP1; see Figure 5 | 9 | ||
| set-up time (nCP0 to nCP1) | tsu | 36 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; nCP0 to nCP1; see Figure 5 | 9 | ||
| set-up time (nCP0 to nCP1) | tsu | 24 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; nCP0 to nCP1; see Figure 5 | 9 | ||
| set-up time (nCP1 to nCP0) | tsu | 60 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; nCP1 to nCP0; see Figure 5 | 9 | ||
| set-up time (nCP1 to nCP0) | tsu | 36 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; nCP1 to nCP0; see Figure 5 | 9 | ||
| set-up time (nCP1 to nCP0) | tsu | 24 | ns | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; nCP1 to nCP0; see Figure 5 | 9 | ||
| maximum frequency | fmax | 6 | MHZ | Tamb=-40℃ to +125℃; VSS=0V; VDD=5V; nCP1, nCP0; see Figure 5 | 9 | ||
| maximum frequency | fmax | 12 | MHZ | Tamb=-40℃ to +125℃; VSS=0V; VDD=10V; nCP1, nCP0; see Figure 5 | 9 | ||
| maximum frequency | fmax | 16 | MHZ | Tamb=-40℃ to +125℃; VSS=0V; VDD=15V; nCP1, nCP0; see Figure 5 | 9 |
CAD (KiCad official)
- Symbol:
CD4520BM - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4520bm-etched.step/cd4520bm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4520bm.step/cd4520bm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (15 pp, sha256
60178b4d605ca8d9, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).