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CD4520BD

Public Made by Adom

by adom

Sungine Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4520BD

Sungine · Counters, Dividers · DIP-16

CD4520BD from Sungine, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK A input Clock input of counter A; counts on the rising edge when ENABLE A is high.
2 ENABLE A input Enable input of counter A; counts on the falling edge when CLOCK A is low.
3 Q1A output Counter A output stage 1.
4 Q2A output Counter A output stage 2.
5 Q3A output Counter A output stage 3.
6 Q4A output Counter A output stage 4, which can be connected to the ENABLE input of the next counter for ripple cascading.
7 RESET A input Reset input of counter A; a high level clears Q1 to Q4 to 0.
8 VSS power_in Ground (0 V) supply pin.
9 CLOCK B input Clock input of counter B; counts on the rising edge when ENABLE B is high.
10 ENABLE B input Enable input of counter B; counts on the falling edge when CLOCK B is low.
11 Q1B output Counter B output stage 1.
12 Q2B output Counter B output stage 2.
13 Q3B output Counter B output stage 3.
14 Q4B output Counter B output stage 4, which can be connected to the ENABLE input of the next counter for ripple cascading.
15 RESET B input Reset input of counter B; a high level clears Q1 to Q4 to 0.
16 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V.

Key specifications

Parameter Value
Manufacturer Sungine
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VDD -0.5 20 V 3
Input voltage VIN -0.5 V 3
Package operating temperature range Tstg -65 150 ℃ 3
Power dissipation PD 700 mW DIP16 package 3
Spot welding temperature TL 300 ℃ 3
Supply voltage (recommended) VDD 3 18 V TA=25℃ 3
Enable pulse width tW 400 ns VDD=5V 4
Enable pulse width tW 200 ns VDD=10V 4
Enable pulse width tW 140 ns VDD=15V 4
Clock pulse width tW 200 ns VDD=5V 4
Clock pulse width tW 100 ns VDD=10V 4
Clock pulse width tW 70 ns VDD=15V 4
Clock input frequency tCL 1.5 MHz VDD=5V 4
Clock input frequency tCL 3 MHz VDD=10V 4
Clock input frequency tCL 4 MHz VDD=15V 4
Reset pulse width tW 250 ns VDD=5V 4
Reset pulse width tW 100 ns VDD=10V 4
Reset pulse width tW 80 ns VDD=15V 4
Propagation delay, clock or enable to output tPHL/tPLH 280 560 ns VDD=5V 5
Propagation delay, clock or enable to output tPHL/tPLH 115 230 ns VDD=10V 5
Propagation delay, clock or enable to output tPHL/tPLH 80 160 ns VDD=15V 5
Reset to output time 330 650 ns VDD=5V 6
Reset to output time 130 225 ns VDD=10V 6
Reset to output time 90 170 ns VDD=15V 6
Transition time tTHL/tTLH 100 200 ns VDD=5V 6
Transition time tTHL/tTLH 50 100 ns VDD=10V 6
Transition time tTHL/tTLH 40 80 ns VDD=15V 6
Maximum input pulse frequency fCL 1.5 3 MHz VDD=5V 6
Maximum input pulse frequency fCL 3 6 MHz VDD=10V 6
Maximum input pulse frequency fCL 4 8 MHz VDD=15V 6
Minimum reset pulse width tW 100 200 ns VDD=5V 6
Minimum reset pulse width tW 50 100 ns VDD=10V 6
Minimum reset pulse width tW 35 70 ns VDD=15V 6
Minimum enable pulse width tW 200 400 ns VDD=5V 6
Minimum enable pulse width tW 100 200 ns VDD=10V 6
Minimum enable pulse width tW 70 140 ns VDD=15V 6
Input capacitance CI 5 7.5 pF any input 6
Quiescent device current IDD 0.04 5 uA VIN=0, VDD=5V; +25℃ 4
Quiescent device current IDD 0.04 10 uA VIN=0, VDD=10V; +25℃ 4
Quiescent device current IDD 0.04 20 uA VIN=0, VDD=15V; +25℃ 4
Quiescent device current IDD 0.08 100 uA VIN=0, VDD=20V; +25℃ 4
Output low (sink) current IOL 0.51 1 mA VO=0.4, VIN=0, VDD=5V; +25℃ 4
Output low (sink) current IOL 1.3 2.8 mA VO=0.5, VIN=0, VDD=10V; +25℃ 4
Output low (sink) current IOL 3.4 6.8 mA VO=1.5, VIN=0, VDD=15V; +25℃ 4
Output high (source) current IOH -0.51 -1 mA VO=4.6, VIN=0, VDD=5V; +25℃ 5
Output high (source) current IOH -1.6 -3.2 mA VO=2.5, VIN=0, VDD=5V; +25℃ 5
Output high (source) current IOH -1.3 -2.6 mA VO=9.5, VIN=0, VDD=10V; +25℃ 5
Output high (source) current IOH -3.4 -6.8 mA VO=13.5, VIN=0, VDD=15V; +25℃ 5
Output low voltage VOL 0 0.05 V VIN=0, VDD=5V; +25℃ 5
Output high voltage VOH 4.95 5 V VIN=0, VDD=5V; +25℃ 5
Output high voltage VOH 9.95 10 V VIN=0, VDD=10V; +25℃ 5
Output high voltage VOH 14.95 15 V VIN=0, VDD=15V; +25℃ 5
Input low voltage VIL 1.5 V VO=0.5/4.5, VDD=5V 5
Input low voltage VIL 3 V VO=1/9, VDD=10V 5
Input low voltage VIL 4 V VO=1.5/13.5, VDD=15V 5
Input high voltage VIH 3.5 V VO=0.5/4.5, VDD=5V 5
Input high voltage VIH 7 V VO=1/9, VDD=10V 5
Input high voltage VIH 11 V VO=1.5/13.5, VDD=15V 5

CAD (KiCad official)

  • Symbol: CD4520BD
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4520bd-etched.step / cd4520bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4520bd.step / cd4520bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (10 pp, sha256 173f9fc2e00d8363, retrieved 2026-10-29, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF