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CD4518BM96

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by adom

Texas Instruments Counters, Dividers, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4518BM96

Texas Instruments · Counters, Dividers · SOIC-16

CD4518BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKA input Clock input for counter A; counter increments on positive CLKA edge when ENABLEA is high, or on negative ENABLEA edge when CLKA is high; max f_CL 3 MHz typ / 6 MHz max at VDD=10 V.
2 ENABLEA input Active-high enable input for counter A; when high, counter increments on positive CLKA edge; when low and CLKA is high, counter increments on falling ENABLEA edge.
3 Q1A output BCD decade counter output Q1 (weight 1, LSB) of counter A; active high, propagation delay 115 ns typ at VDD=10 V.
4 Q2A output BCD decade counter output Q2 (weight 2) of counter A; active high.
5 Q3A output BCD decade counter output Q3 (weight 4) of counter A; active high.
6 Q4A output BCD decade counter output Q4 (weight 8, MSB) of counter A; active high.
7 RESETA input Active-high asynchronous reset input for counter A; forces Q1A-Q4A to logic 0 regardless of clock state; reset pulse width min 55 ns at VDD=10 V.
8 VSS power_in Negative supply voltage (ground) reference; 0 V, lower rail of VDD=3 V to 18 V supply.
9 CLKB input Clock input for counter B; same function as CLKA; counter increments on positive CLKB edge when ENABLEB is high, or on negative ENABLEB edge when CLKB is high.
10 ENABLEB input Active-high enable input for counter B; same function as ENABLEA for the second independent BCD counter section.
11 Q1B output BCD decade counter output Q1 (weight 1, LSB) of counter B; active high.
12 Q2B output BCD decade counter output Q2 (weight 2) of counter B; active high.
13 Q3B output BCD decade counter output Q3 (weight 4) of counter B; active high.
14 Q4B output BCD decade counter output Q4 (weight 8, MSB) of counter B; active high.
15 RESETB input Active-high asynchronous reset input for counter B; forces Q1B-Q4B to logic 0 regardless of clock state; reset pulse width min 55 ns at VDD=10 V.
16 VDD power_in Positive supply voltage; operating range 3 V to 18 V (full package temperature range); absolute maximum 20 V (VDD-VSS).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4518BM96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd4518bm96-etched.step / cd4518bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4518bm96.step / cd4518bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 c28162391ada6d6a, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF