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CD4518BE

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Texas Instruments Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4518BE

Texas Instruments · Counters, Dividers · DIP-16

CD4518BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK A input Clock input of counter A, incrementing on the positive-going transition when ENABLE A is high; clock rise/fall time max 15 µs at 5 V and 5 µs at 10 V and 15 V.
2 ENABLE A input Enable input of counter A, which increments on a negative-going transition when CLOCK A is low; hold high for single-unit operation and connect to Q4 of the preceding counter for ripple cascading.
3 Q1A output Counter A stage 1 output, cleared to 0 when RESET A is high.
4 Q2A output Counter A stage 2 output, cleared to 0 when RESET A is high.
5 Q3A output Counter A stage 3 output, cleared to 0 when RESET A is high.
6 Q4A output Counter A stage 4 output, cleared to 0 when RESET A is high, and can be connected to the enable input of a subsequent counter for ripple cascading.
7 RESET A input Reset input of counter A, which clears Q1 thru Q4 to 0 when high.
8 VSS power_in Ground (negative supply) reference terminal for the device.
9 CLOCK B input Clock input of counter B, incrementing on the positive-going transition when ENABLE B is high; clock rise/fall time max 15 µs at 5 V and 5 µs at 10 V and 15 V.
10 ENABLE B input Enable input of counter B, which increments on a negative-going transition when CLOCK B is low; hold high for single-unit operation and connect to Q4 of the preceding counter for ripple cascading.
11 Q1B output Counter B stage 1 output, cleared to 0 when RESET B is high.
12 Q2B output Counter B stage 2 output, cleared to 0 when RESET B is high.
13 Q3B output Counter B stage 3 output, cleared to 0 when RESET B is high.
14 Q4B output Counter B stage 4 output, cleared to 0 when RESET B is high, and can be connected to the enable input of a subsequent counter for ripple cascading.
15 RESET B input Reset input of counter B, which clears Q1 thru Q4 to 0 when high.
16 VDD power_in Positive supply voltage, recommended 3 V to 18 V over the full package-temperature range with an absolute maximum of -0.5 V to +20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4518BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4518be-etched.step / cd4518be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4518be.step / cd4518be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 c28162391ada6d6a, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF