CD4518BDRG

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4518bdrg",
  "title": "CD4518BDRG",
  "brief": "HANSCHIP semiconductor Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4518bdrg",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "CD4518BDRG",
    "manufacturer": "HANSCHIP semiconductor",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Counters, Dividers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/55b07266060df0a9fb28bc8f7c257b1b.pdf",
    "parts": {
      "symbol": "cd4518bdrg.kicad_sym",
      "footprint": "cd4518bdrg.kicad_mod",
      "model_3d": "cd4518bdrg-etched.glb",
      "model_3d_plain": "cd4518bdrg.glb",
      "model_3d_step": "cd4518bdrg-etched.step",
      "model_3d_step_plain": "cd4518bdrg.step",
      "lbr": "cd4518bdrg.lbr"
    },
    "distributor_links": {
      "lcsc": "C42396709"
    },
    "pins": [
      {
        "number": "1",
        "name": "CLOCK A",
        "type": "input",
        "description": "Clock input for counter A; counter increments on positive-going edge when ENABLE A is high, or on negative-going edge when ENABLE A is held high and clock drives the increment."
      },
      {
        "number": "2",
        "name": "ENABLE A",
        "type": "input",
        "description": "Enable input for counter A; counter advances on positive-going CLOCK transition when ENABLE is high; hold high for single-unit clocked operation."
      },
      {
        "number": "3",
        "name": "Q1A",
        "type": "output",
        "description": "BCD up-counter A stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "4",
        "name": "Q2A",
        "type": "output",
        "description": "BCD up-counter A stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "5",
        "name": "Q3A",
        "type": "output",
        "description": "BCD up-counter A stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "6",
        "name": "Q4A",
        "type": "output",
        "description": "BCD up-counter A stage-4 (MSB) output; connect to ENABLE B for ripple cascading while CLOCK B is held low."
      },
      {
        "number": "7",
        "name": "RESET A",
        "type": "input",
        "description": "Active-high asynchronous reset for counter A; a high level forces Q1A-Q4A to logic 0; minimum reset pulse width 250 ns at VDD = 5 V."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference (0 V); all voltages referenced to this terminal."
      },
      {
        "number": "9",
        "name": "CLOCK B",
        "type": "input",
        "description": "Clock input for counter B; counter increments on positive-going edge when ENABLE B is high; hold low for ripple cascading from Q4A."
      },
      {
        "number": "10",
        "name": "ENABLE B",
        "type": "input",
        "description": "Enable input for counter B; counter advances on positive-going CLOCK B transition when high; used as ripple-cascade input driven by Q4A."
      },
      {
        "number": "11",
        "name": "Q1B",
        "type": "output",
        "description": "BCD up-counter B stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "12",
        "name": "Q2B",
        "type": "output",
        "description": "BCD up-counter B stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "13",
        "name": "Q3B",
        "type": "output",
        "description": "BCD up-counter B stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."
      },
      {
        "number": "14",
        "name": "Q4B",
        "type": "output",
        "description": "BCD up-counter B stage-4 (MSB) output; connect to ENABLE of subsequent counter for ripple cascading."
      },
      {
        "number": "15",
        "name": "RESET B",
        "type": "input",
        "description": "Active-high asynchronous reset for counter B; a high level forces Q1B-Q4B to logic 0; minimum reset pulse width 250 ns at VDD = 5 V."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply voltage; operating range -0.5 V to +20 V (absolute maximum); parametric ratings at 5 V, 10 V and 15 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-4-6",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-7",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 14,
        "cost_usd": 0.3855,
        "at": "2026-09-18T02:44:35"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/55b07266060df0a9fb28bc8f7c257b1b.pdf",
        "pages": 14,
        "sha256": "54370e3d6c4be386",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4518bdrg.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4518bdrg-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "19ca50d775379cd2f1d6d76adf0ee7541546a93912cd584e358475b3709b7179",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HANSCHIP semiconductor",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4518bdrg"
  ],
  "discovery_pitch": "CD4518BDRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4518bdrg.kicad_sym",
    "cd4518bdrg.kicad_mod",
    "cd4518bdrg.glb",
    "cd4518bdrg.step",
    "cd4518bdrg.lbr",
    "docs/hero.png",
    "docs/cd4518bdrg-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:51:23.385Z"
}