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Contents

README

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CD4518BD

Sungine · Counters, Dividers · DIP-16

CD4518BD from Sungine, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK A input Clock input of counter A, advancing the count on a rising edge when ENABLE A is high.
2 ENABLE A input Enable input of counter A, advancing the count on a falling edge when CLOCK A is low.
3 Q1A output Counter A stage 1 output.
4 Q2A output Counter A stage 2 output.
5 Q3A output Counter A stage 3 output.
6 Q4A output Counter A stage 4 output, which can drive the ENABLE input of the next counter for ripple cascading.
7 RESET A input Reset input of counter A, which clears Q1 to Q4 to 0 when high.
8 VSS power_in Ground (0 V) supply pin.
9 CLOCK B input Clock input of counter B, advancing the count on a rising edge when ENABLE B is high.
10 ENABLE B input Enable input of counter B, advancing the count on a falling edge when CLOCK B is low.
11 Q1B output Counter B stage 1 output.
12 Q2B output Counter B stage 2 output.
13 Q3B output Counter B stage 3 output.
14 Q4B output Counter B stage 4 output, which can drive the ENABLE input of the next counter for ripple cascading.
15 RESET B input Reset input of counter B, which clears Q1 to Q4 to 0 when high.
16 VDD power_in Positive supply pin, recommended 3 V to 18 V with an absolute maximum of -0.5 V to +20 V.

Key specifications

Parameter Value
Manufacturer Sungine
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 20 V 3
Input voltage VIN -0.5 V -0.5 to VCC+0.5 3
Storage temperature Tstg -65 150 °C 3
Power dissipation PD 700 mW DIP16 3
Soldering temperature TL 300 °C 3
Supply voltage VDD 3 18 V TA=25°C 4
Quiescent device current IDD 0.04 5 uA VIN=0,5; VDD=5V; +25°C 4
Quiescent device current IDD 0.04 10 uA VIN=0,10; VDD=10V; +25°C 4
Quiescent device current IDD 0.04 20 uA VIN=0,15; VDD=15V; +25°C 4
Quiescent device current IDD 0.08 100 uA VIN=0,20; VDD=20V; +25°C 4
Quiescent device current IDD 150 uA VIN=0,5; VDD=5V; +125°C 4
Quiescent device current IDD 300 uA VIN=0,10; VDD=10V; +125°C 4
Quiescent device current IDD 600 uA VIN=0,15; VDD=15V; +125°C 4
Quiescent device current IDD 3000 uA VIN=0,20; VDD=20V; +125°C 4
Output low (sink) current IOL 0.51 1 mA VO=0.4V; VIN=0,5; VDD=5V; +25°C 4
Output low (sink) current IOL 1.3 2.8 mA VO=0.5V; VIN=0,10; VDD=10V; +25°C 4
Output low (sink) current IOL 3.4 6.8 mA VO=1.5V; VIN=0,15; VDD=15V; +25°C 4
Output high (source) current IOH -0.51 -1 mA VO=4.6V; VIN=0,5; VDD=5V; +25°C 5
Output high (source) current IOH -1.6 -3.2 mA VO=2.5V; VIN=0,5; VDD=5V; +25°C 5
Output high (source) current IOH -1.3 -2.6 mA VO=9.5V; VIN=0,10; VDD=10V; +25°C 5
Output high (source) current IOH -3.4 -6.8 mA VO=13.5V; VIN=0,15; VDD=15V; +25°C 5
Output low voltage VOL 0 0.05 V VIN=0,5; VDD=5V 5
Output high voltage VOH 4.95 5 V VIN=0,5; VDD=5V; +25°C 5
Output high voltage VOH 9.95 10 V VIN=0,10; VDD=10V; +25°C 5
Output high voltage VOH 14.95 15 V VIN=0,15; VDD=15V; +25°C 5
Input low voltage VIL 1.5 V VO=0.5,4.5; VDD=5V; +25°C 5
Input low voltage VIL 3 V VO=1,9; VDD=10V; +25°C 5
Input low voltage VIL 4 V VO=1.5,13.5; VDD=15V; +25°C 5
Input high voltage VIH 3.5 V VO=0.5,4.5; VDD=5V; +25°C 5
Input high voltage VIH 7 V VO=1,9; VDD=10V; +25°C 5
Input high voltage VIH 11 V VO=1.5,13.5; VDD=15V; +25°C 5
Input current IIN -0.1 0.1 uA VIN=0,18; VDD=18V; +25°C 5
Propagation delay, clock or enable to output tPHL/tPLH 280 560 ns VDD=5V; TA=25°C 5
Propagation delay, clock or enable to output tPHL/tPLH 115 230 ns VDD=10V; TA=25°C 5
Propagation delay, clock or enable to output tPHL/tPLH 80 160 ns VDD=15V; TA=25°C 6
Propagation delay, reset to output tPHL/tPLH 330 650 ns VDD=5V; TA=25°C 6
Propagation delay, reset to output tPHL/tPLH 130 225 ns VDD=10V; TA=25°C 6
Propagation delay, reset to output tPHL/tPLH 90 170 ns VDD=15V; TA=25°C 6
Transition time tTHL/tTLH 100 200 ns VDD=5V; TA=25°C 6
Transition time tTHL/tTLH 50 100 ns VDD=10V; TA=25°C 6
Transition time tTHL/tTLH 40 80 ns VDD=15V; TA=25°C 6
Maximum input clock frequency fCL 1.5 3 MHz VDD=5V; TA=25°C 6
Maximum input clock frequency fCL 3 6 MHz VDD=10V; TA=25°C 6
Maximum input clock frequency fCL 4 8 MHz VDD=15V; TA=25°C 6
Minimum reset pulse width tW 100 200 ns VDD=5V; TA=25°C 6
Minimum reset pulse width tW 50 100 ns VDD=10V; TA=25°C 6
Minimum reset pulse width tW 35 70 ns VDD=15V; TA=25°C 6
Minimum enable pulse width tW 200 400 ns VDD=5V; TA=25°C 6
Minimum enable pulse width tW 100 200 ns VDD=10V; TA=25°C 6
Minimum enable pulse width tW 70 140 ns VDD=15V; TA=25°C 6
Input capacitance CI 5 7.5 pF Any input 6

CAD (KiCad official)

  • Symbol: CD4518BD
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4518bd-etched.step / cd4518bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4518bd.step / cd4518bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (10 pp, sha256 9863ed8de041780f, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF