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CD4517BE

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Texas Instruments Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4517BE

Texas Instruments · Shift Registers · DIP-16

CD4517BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q16A bidirectional Register A stage-16 tap: 3-state output (WE=0) that becomes the data input to the 17th stage when WE=1 and the clock goes low-to-high.
2 Q48A bidirectional Register A stage-48 tap: 3-state output (WE=0) that becomes the data input to the 49th stage when WE=1 and the clock goes low-to-high.
3 WEA input Register A write enable: logic 1 with a clock low-to-high transition enters data at the 17th, 33rd and 49th stages and puts the taps in high impedance.
4 CLA input Register A clock input (Schmitt trigger, tolerates very slow rise and fall times); shifts on the low-to-high transition.
5 Q64A tri_state Register A stage-64 3-state output, high impedance when WE=1.
6 Q32A bidirectional Register A stage-32 tap: 3-state output (WE=0) that becomes the data input to the 33rd stage when WE=1 and the clock goes low-to-high.
7 DA input Register A serial data input to the first stage.
8 VSS power_in Ground (negative supply) terminal; VDD voltages are referenced to it.
9 DB input Register B serial data input to the first stage.
10 Q32B bidirectional Register B stage-32 tap: 3-state output (WE=0) that becomes the data input to the 33rd stage when WE=1 and the clock goes low-to-high.
11 Q64B tri_state Register B stage-64 3-state output, high impedance when WE=1.
12 CLB input Register B clock input (Schmitt trigger, tolerates very slow rise and fall times); shifts on the low-to-high transition.
13 WEB input Register B write enable: logic 1 with a clock low-to-high transition enters data at the 17th, 33rd and 49th stages and puts the taps in high impedance.
14 Q48B bidirectional Register B stage-48 tap: 3-state output (WE=0) that becomes the data input to the 49th stage when WE=1 and the clock goes low-to-high.
15 Q16B bidirectional Register B stage-16 tap: 3-state output (WE=0) that becomes the data input to the 17th stage when WE=1 and the clock goes low-to-high.
16 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4517BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4517be-etched.step / cd4517be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4517be.step / cd4517be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 19fb9c4c035e6cb4, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF