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Initial commit: component/cd4516bpwr

Ray ·dfbf6b00e8 ·
2 files changed +243
README.mdadded+52
@@ -0,0 +1,52 @@+# CD4516BPWR++**Texas Instruments** · Counters, Dividers · TSSOP-16++CD4516BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PRESET ENABLE | input | Active-high input that asynchronously loads the parallel jam inputs P1-P4 into the counter, overriding clock and count operation. |+| 2 | Q4 | output | Q4 counter output, the most significant bit of the 4-bit up/down counter. |+| 3 | P4 | input | Parallel jam (preset) data input for the most significant counter stage, loaded into the counter when PRESET ENABLE is high. |+| 4 | P1 | input | Parallel jam (preset) data input for the least significant counter stage, loaded into the counter when PRESET ENABLE is high. |+| 5 | CARRY IN | input | Active-low carry-in input that must be held low to permit synchronous up/down counting and is used to cascade the carry chain from a less significant stage. |+| 6 | Q1 | output | Q1 counter output, the least significant bit of the 4-bit up/down counter. |+| 7 | CARRY OUT | output | Active-low carry-out output that goes low at the terminal count to ripple-cascade to the carry-in of the next counter stage. |+| 8 | VSS | power_in | Negative supply/ground reference terminal. |+| 9 | RESET | input | Active-high asynchronous reset input; a high level clears all counter outputs Q1-Q4 to zero, overriding preset and clock. |+| 10 | UP/DOWN | input | Count-direction control input; a high level selects count-up operation and a low level selects count-down operation (per truth table). |+| 11 | Q2 | output | Q2 counter output bit. |+| 12 | P2 | input | Parallel jam (preset) data input for counter bit 2, loaded into the counter when PRESET ENABLE is high. |+| 13 | P3 | input | Parallel jam (preset) data input for counter bit 3, loaded into the counter when PRESET ENABLE is high. |+| 14 | Q3 | output | Q3 counter output bit. |+| 15 | CLOCK | input | Clock input; the counter advances on the positive-going (low-to-high) transition of this signal when enabled by carry-in. |+| 16 | VDD | power_in | Positive supply-voltage terminal, specified over a 3 V to 18 V supply range (20 V absolute maximum) referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4516BPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4516bpwr-etched.step` / `cd4516bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4516bpwr.step` / `cd4516bpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4516b.pdf) (20 pp, sha256 `fc185675c565180b`, retrieved 2026-09-23, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4516bpwr-datasheet.pdf)
page.jsonadded+191
@@ -0,0 +1,191 @@+{+  "slug": "cd4516bpwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Counters, Dividers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4516bpwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4516bpwr.kicad_sym",+    "cd4516bpwr.kicad_mod",+    "cd4516bpwr.glb",+    "cd4516bpwr.step",+    "cd4516bpwr.lbr",+    "docs/hero.png",+    "docs/cd4516bpwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "CD4516BPWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Counters, Dividers",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4516b.pdf",+    "parts": {+      "symbol": "cd4516bpwr.kicad_sym",+      "footprint": "cd4516bpwr.kicad_mod",+      "model_3d": "cd4516bpwr-etched.glb",+      "model_3d_plain": "cd4516bpwr.glb",+      "model_3d_step": "cd4516bpwr-etched.step",+      "model_3d_step_plain": "cd4516bpwr.step",+      "lbr": "cd4516bpwr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2653015"+    },+    "pins": [+      {+        "number": "1",+        "name": "PRESET ENABLE",+        "type": "input",+        "description": "Active-high input that asynchronously loads the parallel jam inputs P1-P4 into the counter, overriding clock and count operation."+      },+      {+        "number": "2",+        "name": "Q4",+        "type": "output",+        "description": "Q4 counter output, the most significant bit of the 4-bit up/down counter."+      },+      {+        "number": "3",+        "name": "P4",+        "type": "input",+        "description": "Parallel jam (preset) data input for the most significant counter stage, loaded into the counter when PRESET ENABLE is high."+      },+      {+        "number": "4",+        "name": "P1",+        "type": "input",+        "description": "Parallel jam (preset) data input for the least significant counter stage, loaded into the counter when PRESET ENABLE is high."+      },+      {+        "number": "5",+        "name": "CARRY IN",+        "type": "input",+        "description": "Active-low carry-in input that must be held low to permit synchronous up/down counting and is used to cascade the carry chain from a less significant stage."+      },+      {+        "number": "6",+        "name": "Q1",+        "type": "output",+        "description": "Q1 counter output, the least significant bit of the 4-bit up/down counter."+      },+      {+        "number": "7",+        "name": "CARRY OUT",+        "type": "output",+        "description": "Active-low carry-out output that goes low at the terminal count to ripple-cascade to the carry-in of the next counter stage."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply/ground reference terminal."+      },+      {+        "number": "9",+        "name": "RESET",+        "type": "input",+        "description": "Active-high asynchronous reset input; a high level clears all counter outputs Q1-Q4 to zero, overriding preset and clock."+      },+      {+        "number": "10",+        "name": "UP/DOWN",+        "type": "input",+        "description": "Count-direction control input; a high level selects count-up operation and a low level selects count-down operation (per truth table)."+      },+      {+        "number": "11",+        "name": "Q2",+        "type": "output",+        "description": "Q2 counter output bit."+      },+      {+        "number": "12",+        "name": "P2",+        "type": "input",+        "description": "Parallel jam (preset) data input for counter bit 2, loaded into the counter when PRESET ENABLE is high."+      },+      {+        "number": "13",+        "name": "P3",+        "type": "input",+        "description": "Parallel jam (preset) data input for counter bit 3, loaded into the counter when PRESET ENABLE is high."+      },+      {+        "number": "14",+        "name": "Q3",+        "type": "output",+        "description": "Q3 counter output bit."+      },+      {+        "number": "15",+        "name": "CLOCK",+        "type": "input",+        "description": "Clock input; the counter advances on the positive-going (low-to-high) transition of this signal when enabled by carry-in."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply-voltage terminal, specified over a 3 V to 18 V supply range (20 V absolute maximum) referenced to VSS."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-sonnet-5",+        "primary_mode": "vision",+        "consensus_model": "claude-opus-4-8",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "vision extraction: provenance cannot be text-verified; needs consensus"+        ],+        "pages_sent": 12,+        "cost_usd": 0.6172,+        "at": "2026-09-23T18:47:42"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4516b.pdf",+        "pages": 20,+        "sha256": "fc185675c565180b",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file