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CD4516BPWR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4516BPWR
Texas Instruments · Counters, Dividers · TSSOP-16
CD4516BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PRESET ENABLE | input | Active-high input that asynchronously loads the parallel jam inputs P1-P4 into the counter, overriding clock and count operation. |
| 2 | Q4 | output | Q4 counter output, the most significant bit of the 4-bit up/down counter. |
| 3 | P4 | input | Parallel jam (preset) data input for the most significant counter stage, loaded into the counter when PRESET ENABLE is high. |
| 4 | P1 | input | Parallel jam (preset) data input for the least significant counter stage, loaded into the counter when PRESET ENABLE is high. |
| 5 | CARRY IN | input | Active-low carry-in input that must be held low to permit synchronous up/down counting and is used to cascade the carry chain from a less significant stage. |
| 6 | Q1 | output | Q1 counter output, the least significant bit of the 4-bit up/down counter. |
| 7 | CARRY OUT | output | Active-low carry-out output that goes low at the terminal count to ripple-cascade to the carry-in of the next counter stage. |
| 8 | VSS | power_in | Negative supply/ground reference terminal. |
| 9 | RESET | input | Active-high asynchronous reset input; a high level clears all counter outputs Q1-Q4 to zero, overriding preset and clock. |
| 10 | UP/DOWN | input | Count-direction control input; a high level selects count-up operation and a low level selects count-down operation (per truth table). |
| 11 | Q2 | output | Q2 counter output bit. |
| 12 | P2 | input | Parallel jam (preset) data input for counter bit 2, loaded into the counter when PRESET ENABLE is high. |
| 13 | P3 | input | Parallel jam (preset) data input for counter bit 3, loaded into the counter when PRESET ENABLE is high. |
| 14 | Q3 | output | Q3 counter output bit. |
| 15 | CLOCK | input | Clock input; the counter advances on the positive-going (low-to-high) transition of this signal when enabled by carry-in. |
| 16 | VDD | power_in | Positive supply-voltage terminal, specified over a 3 V to 18 V supply range (20 V absolute maximum) referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4516BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4516bpwr-etched.step/cd4516bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4516bpwr.step/cd4516bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
fc185675c565180b, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).