# CD4510BPWR

**Texas Instruments** · Logic ICs · TSSOP-16

CD4510BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PRESET ENABLE | input | A high level on this line presets the counter to the binary number present on the jam inputs P1-P4. |
| 2 | Q4 | output | Buffered counter output Q4 (fourth flip-flop). |
| 3 | P4 | input | Jam (preset) input 4, loaded into the counter when PRESET ENABLE is high. |
| 4 | P1 | input | Jam (preset) input 1, loaded into the counter when PRESET ENABLE is high. |
| 5 | CARRY IN | input | Active-low carry input; when held low the counter advances up or down on each positive-going clock transition. |
| 6 | Q1 | output | Buffered counter output Q1 (first flip-flop). |
| 7 | CARRY OUT | output | Active-low carry output, connected to CARRY IN of the next more significant stage for synchronous cascading or to the clock of the next stage for ripple cascading. |
| 8 | VSS | power_in | Ground / negative supply terminal; all voltages are referenced to VSS. |
| 9 | RESET | input | A high level on this line clears the counter. |
| 10 | UP/DOWN | input | Selects the count direction (up or down); should change only while the clock is high if CARRY OUT is used for ripple cascading. |
| 11 | Q2 | output | Buffered counter output Q2 (second flip-flop). |
| 12 | P2 | input | Jam (preset) input 2, loaded into the counter when PRESET ENABLE is high. |
| 13 | P3 | input | Jam (preset) input 3, loaded into the counter when PRESET ENABLE is high. |
| 14 | Q3 | output | Buffered counter output Q3 (third flip-flop). |
| 15 | CLOCK | input | Clock input; the counter advances on the positive-going clock transition (max clock input frequency 2/4/5.5 MHz at 5/10/15 V). |
| 16 | VDD | power_in | Positive supply voltage, 3 V to 18 V recommended, absolute maximum -0.5 V to +20 V referenced to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `CD4510BPWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4510bpwr-etched.step` / `cd4510bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4510bpwr.step` / `cd4510bpwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4510b.pdf) (20 pp, sha256 `fc185675c565180b`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4510bpwr-datasheet.pdf)