component
CD4510B BCD Up/Down Counter
Public Made by Adomby adom
Presettable BCD up/down counter in the 4000B CMOS family, 3 V to 18 V.
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page.json+168−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4510",+ "title": "CD4510B BCD Up/Down Counter",+ "brief": "Presettable BCD up/down counter in the 4000B CMOS family, 3 V to 18 V.", "version": "0.1.0",- "type": "component",- "description": "Presettable BCD up/down counter in the 4000B CMOS family, 3 V to 18 V.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "counter",@@ -12,6 +15,168 @@ "ti", "soic-16" ],+ "component": {+ "mpn": "CD4510B",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counter",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4510b.pdf",+ "parts": {+ "symbol": "cd4510.kicad_sym",+ "footprint": "cd4510.kicad_mod",+ "model_3d": "cd4510.glb",+ "model_3d_step": "cd4510.step"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "PRESET_ENABLE",+ "type": "input",+ "description": "Preset (parallel-load) enable. When held high, the counter is asynchronously loaded with the BCD value on P1-P4; must be low for normal counting."+ },+ {+ "number": "2",+ "name": "Q4",+ "type": "output",+ "description": "Counter output bit 4 (MSB of the BCD count)."+ },+ {+ "number": "3",+ "name": "P4",+ "type": "input",+ "description": "Jam / parallel-load data input, bit 4 (MSB of the BCD preset word). Sampled into the fourth flip-flop while PRESET ENABLE is high."+ },+ {+ "number": "4",+ "name": "P1",+ "type": "input",+ "description": "Jam / parallel-load data input, bit 1 (LSB of the BCD preset word). Sampled into the first flip-flop while PRESET ENABLE is high."+ },+ {+ "number": "5",+ "name": "~{CARRY_IN}",+ "type": "input",+ "description": "Active-low carry-in from a less-significant stage. When held low the counter advances on each positive clock edge; when high the counter is inhibited. Tie to VSS when this stage is used stand-alone."+ },+ {+ "number": "6",+ "name": "Q1",+ "type": "output",+ "description": "Counter output bit 1 (LSB of the BCD count)."+ },+ {+ "number": "7",+ "name": "~{CARRY_OUT}",+ "type": "output",+ "description": "Active-low ripple/synchronous carry-out. Goes low on the terminal count so the next stage's CARRY IN can enable it, allowing synchronous or ripple cascading of multiple CD4510B counters."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground / negative supply reference (0 V). All input and supply voltages are referenced to this pin."+ },+ {+ "number": "9",+ "name": "RESET",+ "type": "input",+ "description": "Active-high asynchronous master reset. Forces all Q outputs to logic 0 while held high; must be low for normal counting or preset operation."+ },+ {+ "number": "10",+ "name": "UP/DOWN",+ "type": "input",+ "description": "Count-direction control. High selects up-count (0-9 with a maximum of two clock pulses of non-BCD states after preset), low selects down-count. May be changed at any count in ripple-clock mode provided the first-stage clock is high."+ },+ {+ "number": "11",+ "name": "Q2",+ "type": "output",+ "description": "Counter output bit 2."+ },+ {+ "number": "12",+ "name": "P2",+ "type": "input",+ "description": "Jam / parallel-load data input, bit 2. Sampled into the second flip-flop while PRESET ENABLE is high."+ },+ {+ "number": "13",+ "name": "P3",+ "type": "input",+ "description": "Jam / parallel-load data input, bit 3. Sampled into the third flip-flop while PRESET ENABLE is high."+ },+ {+ "number": "14",+ "name": "Q3",+ "type": "output",+ "description": "Counter output bit 3."+ },+ {+ "number": "15",+ "name": "CLOCK",+ "type": "input",+ "description": "Positive-edge triggered clock input. Typical maximum clock frequency 2 MHz at 5 V, 4 MHz at 10 V, 5.5 MHz at 15 V (8 MHz typical at 10 V). Rise/fall time should be <=15 us at 5 V, <=5 us at 10-15 V."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage, 3 V to 18 V (parametric ratings at 5 V, 10 V, 15 V). Bypass to VSS with a ceramic capacitor."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4510b.pdf",+ "pages": 20,+ "sha256": "41f1a4f20347ef51",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "Presettable BCD up/down counter",+ "Logic family": "4000B (CMOS)",+ "Count": "BCD (0-9), up or down",+ "Features": "Parallel preset, carry in/out, cascadable",+ "Supply voltage": "3 V to 18 V",+ "Operating temperature": "-55 C to 125 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "BCD counter",+ "up down counter",+ "presettable counter",+ "decade counter"+ ],+ "discovery_pitch": "A presettable BCD counter that counts up or down and cascades for multi-digit counting.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -28,10 +193,5 @@ "docs/cd4510-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }