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CD4510B BCD Up/Down Counter

Public Made by Adom

by adom

Presettable BCD up/down counter in the 4000B CMOS family, 3 V to 18 V.

logiccounterbcdup-down4000-seriestisoic-16
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Contents

README

markdown

CD4510B

Texas Instruments · Counter · SOIC-16

The CD4510B is a presettable BCD (decade) up/down counter. A direction input selects counting up or down, parallel jam inputs preset the count, and carry-in/carry-out allow cascading into multi-digit counters. It runs from 3 V to 18 V.

Pinout

Pin Name Type Function
1 PRESET_ENABLE input Preset (parallel-load) enable. When held high, the counter is asynchronously loaded with the BCD value on P1-P4; must be low for normal counting.
2 Q4 output Counter output bit 4 (MSB of the BCD count).
3 P4 input Jam / parallel-load data input, bit 4 (MSB of the BCD preset word). Sampled into the fourth flip-flop while PRESET ENABLE is high.
4 P1 input Jam / parallel-load data input, bit 1 (LSB of the BCD preset word). Sampled into the first flip-flop while PRESET ENABLE is high.
5 ~{CARRY_IN} input Active-low carry-in from a less-significant stage. When held low the counter advances on each positive clock edge; when high the counter is inhibited. Tie to VSS when this stage is used stand-alone.
6 Q1 output Counter output bit 1 (LSB of the BCD count).
7 ~{CARRY_OUT} output Active-low ripple/synchronous carry-out. Goes low on the terminal count so the next stage's CARRY IN can enable it, allowing synchronous or ripple cascading of multiple CD4510B counters.
8 VSS power_in Ground / negative supply reference (0 V). All input and supply voltages are referenced to this pin.
9 RESET input Active-high asynchronous master reset. Forces all Q outputs to logic 0 while held high; must be low for normal counting or preset operation.
10 UP/DOWN input Count-direction control. High selects up-count (0-9 with a maximum of two clock pulses of non-BCD states after preset), low selects down-count. May be changed at any count in ripple-clock mode provided the first-stage clock is high.
11 Q2 output Counter output bit 2.
12 P2 input Jam / parallel-load data input, bit 2. Sampled into the second flip-flop while PRESET ENABLE is high.
13 P3 input Jam / parallel-load data input, bit 3. Sampled into the third flip-flop while PRESET ENABLE is high.
14 Q3 output Counter output bit 3.
15 CLOCK input Positive-edge triggered clock input. Typical maximum clock frequency 2 MHz at 5 V, 4 MHz at 10 V, 5.5 MHz at 15 V (8 MHz typical at 10 V). Rise/fall time should be <=15 us at 5 V, <=5 us at 10-15 V.
16 VDD power_in Positive supply voltage, 3 V to 18 V (parametric ratings at 5 V, 10 V, 15 V). Bypass to VSS with a ceramic capacitor.

Key specifications

Parameter Value
Type Presettable BCD up/down counter
Logic family 4000B (CMOS)
Count BCD (0-9), up or down
Features Parallel preset, carry in/out, cascadable
Supply voltage 3 V to 18 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4510BE
  • CD4510BBE
  • CD4510BNSR
  • CD4510BBNSR
  • CD4510BPWR
  • CD4510BBPWR
  • CD4510BF3A

CAD (KiCad official)

  • Symbol: cd4510.kicad_sym
  • Footprint: cd4510.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.
  • 3D model files: cd4510-etched.step / cd4510-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4510.step / cd4510.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 41f1a4f20347ef51, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF