# CD4508BM96

**Texas Instruments** · Latches · SOIC-24

CD4508BM96 from Texas Instruments, in a SOIC-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET A | input | Master reset for latch A; a high level forces the A outputs low regardless of strobe state. |
| 2 | STROBE A | input | Strobe for latch A; high passes D data to Q outputs, a low level latches the data. |
| 3 | OUTPUT DISABLE A | input | A high level forces the A outputs to the high-impedance state; low enables them. |
| 4 | D0A | input | Data input 0 of latch A. |
| 5 | Q0A | tri_state | 3-state output 0 of latch A, high-impedance when OUTPUT DISABLE A is high. |
| 6 | D1A | input | Data input 1 of latch A. |
| 7 | Q1A | tri_state | 3-state output 1 of latch A, high-impedance when OUTPUT DISABLE A is high. |
| 8 | D2A | input | Data input 2 of latch A. |
| 9 | Q2A | tri_state | 3-state output 2 of latch A, high-impedance when OUTPUT DISABLE A is high. |
| 10 | D3A | input | Data input 3 of latch A. |
| 11 | Q3A | tri_state | 3-state output 3 of latch A, high-impedance when OUTPUT DISABLE A is high. |
| 12 | VSS | power_in | Ground / negative supply terminal; VDD voltages are referenced to it. |
| 13 | RESET B | input | Master reset for latch B; a high level forces the B outputs low regardless of strobe state. |
| 14 | STROBE B | input | Strobe for latch B; high passes D data to Q outputs, a low level latches the data. |
| 15 | OUTPUT DISABLE B | input | A high level forces the B outputs to the high-impedance state; low enables them. |
| 16 | D0B | input | Data input 0 of latch B. |
| 17 | Q0B | tri_state | 3-state output 0 of latch B, high-impedance when OUTPUT DISABLE B is high. |
| 18 | D1B | input | Data input 1 of latch B. |
| 19 | Q1B | tri_state | 3-state output 1 of latch B, high-impedance when OUTPUT DISABLE B is high. |
| 20 | D2B | input | Data input 2 of latch B. |
| 21 | Q2B | tri_state | 3-state output 2 of latch B, high-impedance when OUTPUT DISABLE B is high. |
| 22 | D3B | input | Data input 3 of latch B. |
| 23 | Q3B | tri_state | 3-state output 3 of latch B, high-impedance when OUTPUT DISABLE B is high. |
| 24 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-24 |
| Category | Logic |
| Pins | 24 |

## CAD (KiCad official)

- Symbol: `CD4508BM96`
- Footprint: `Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm`
- 3D model: SOIC-24 (KiCad packages3D, STEP)
- 3D model files: `cd4508bm96-etched.step` / `cd4508bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4508bm96.step` / `cd4508bm96.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4508b) (16 pp, sha256 `a3b13b6b5b7a8eda`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4508bm96-datasheet.pdf)