# CD4094BPWR

**Texas Instruments** · Shift Registers · TSSOP-16

CD4094BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STROBE | input | Strobe input; when high, transfers data from the 8-stage shift register into the associated 8-bit storage register. |
| 2 | DATA | input | Serial data input to the first shift-register stage; data is shifted into the register on positive clock transitions. |
| 3 | CLOCK | input | Clock input that shifts data through the 8-stage register on positive-going transitions. |
| 4 | Q1 | tri_state | 3-state buffered parallel output of shift-register stage 1, driven from the storage register and enabled by OUTPUT ENABLE. |
| 5 | Q2 | tri_state | 3-state buffered parallel output of shift-register stage 2, driven from the storage register and enabled by OUTPUT ENABLE. |
| 6 | Q3 | tri_state | 3-state buffered parallel output of shift-register stage 3, driven from the storage register and enabled by OUTPUT ENABLE. |
| 7 | Q4 | tri_state | 3-state buffered parallel output of shift-register stage 4, driven from the storage register and enabled by OUTPUT ENABLE. |
| 8 | VSS | power_in | Negative supply / ground reference terminal; all other pin voltages are referenced to VSS. |
| 9 | QS | output | Serial output synchronous to the positive clock edge, used for cascading CD4094B devices in high-speed systems with fast clock rise time. |
| 10 | Q'S | output | Serial output synchronous to the negative clock edge, providing the same serial information as QS for cascading devices when clock rise time is slow. |
| 11 | Q8 | tri_state | 3-state buffered parallel output of shift-register stage 8, driven from the storage register and enabled by OUTPUT ENABLE. |
| 12 | Q7 | tri_state | 3-state buffered parallel output of shift-register stage 7, driven from the storage register and enabled by OUTPUT ENABLE. |
| 13 | Q6 | tri_state | 3-state buffered parallel output of shift-register stage 6, driven from the storage register and enabled by OUTPUT ENABLE. |
| 14 | Q5 | tri_state | 3-state buffered parallel output of shift-register stage 5, driven from the storage register and enabled by OUTPUT ENABLE. |
| 15 | OUTPUT ENABLE | input | Output-enable control input; when high, the data in the storage register appears at the Q1-Q8 parallel outputs, otherwise the outputs are placed in the high-impedance (open-circuit) state. |
| 16 | VDD | power_in | Positive supply-voltage pin, referenced to VSS, with a recommended operating range of 3 V to 18 V (absolute maximum -0.5 V to +20 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `CD4094BPWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4094bpwr-etched.step` / `cd4094bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4094bpwr.step` / `cd4094bpwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4094b.pdf) (18 pp, sha256 `52741c14b853b678`, retrieved 2026-09-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4094bpwr-datasheet.pdf)