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CD4094BM

Public Made by Adom

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lingxingic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4094BM

lingxingic · Shift Registers · SOP-16

CD4094BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STR input Strobe input: when HIGH, the data in each shift register stage is transferred to the storage register.
2 D input Serial data input, shifted into the first register stage on positive-going clock transitions.
3 CP input Clock input; data is shifted on positive-going clock transitions.
4 QP0 tri_state Parallel 3-state output from storage register stage 0, active when OE is HIGH and high-impedance when OE is LOW.
5 QP1 tri_state Parallel 3-state output from storage register stage 1, active when OE is HIGH and high-impedance when OE is LOW.
6 QP2 tri_state Parallel 3-state output from storage register stage 2, active when OE is HIGH and high-impedance when OE is LOW.
7 QP3 tri_state Parallel 3-state output from storage register stage 3, active when OE is HIGH and high-impedance when OE is LOW.
8 VSS power_in Ground (0 V) reference for all voltages; supply range is 3 V to 15 V referenced to VSS.
9 QS1 output Serial output giving the stage 6 data on positive-going clock edges, for high-speed cascading.
10 QS2 output Serial output giving the same data as QS1 on the next negative-going clock edge, for cascading when the clock has a slow rise time.
11 QP7 tri_state Parallel 3-state output from storage register stage 7, active when OE is HIGH and high-impedance when OE is LOW.
12 QP6 tri_state Parallel 3-state output from storage register stage 6, active when OE is HIGH and high-impedance when OE is LOW.
13 QP5 tri_state Parallel 3-state output from storage register stage 5, active when OE is HIGH and high-impedance when OE is LOW.
14 QP4 tri_state Parallel 3-state output from storage register stage 4, active when OE is HIGH and high-impedance when OE is LOW.
15 OE input Output enable input: storage register data appears at the parallel outputs whenever OE is HIGH; outputs are high-impedance when LOW.
16 VDD power_in Positive supply voltage, recommended range 3 V to 15 V referenced to VSS; absolute maximum is 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 6
DC input current IIK -10 10 mA any one input 6
input voltage VI -0.5 V all inputs 6
storage temperature Tstg -65 150 ℃ 6
total power dissipation Ptot 500 mW 6
device dissipation per output transistor P 100 mW per output transistor 6
soldering temperature TL 250 ℃ 10s, SOP 6
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 85 ℃ in free air 6
data setup time tsu 125 ns VDD=5V 6
data setup time tsu 55 ns VDD=10V 6
data setup time tsu 35 ns VDD=15V 6
clock pulse width tw 200 ns VDD=5V 6
clock pulse width tw 100 ns VDD=10V 6
clock pulse width tw 83 ns VDD=15V 6
clock input frequency fmax 1.25 MHz VDD=5V 7
clock input frequency fmax 2.5 MHz VDD=10V 7
clock input frequency fmax 3 MHz VDD=15V 7
clock rise and fall time trCL, tfCL 15 us VDD=5V 7
clock rise and fall time trCL, tfCL 5 us VDD=10V 7
strobe setup time tw 200 ns VDD=5V 7
strobe setup time tw 80 ns VDD=10V 7
strobe setup time tw 70 ns VDD=15V 7
supply current IDD 0.04 5 uA VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
supply current IDD 0.04 10 uA VIN=0, 10 V; VDD=10 V; Tamb=25℃ 7
supply current IDD 0.04 20 uA VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
LOW-level output current IOL 0.51 1 mA VO=0.4 V; VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
LOW-level output current IOL 1.3 2.6 mA VO=0.5 V; VIN=0, 10 V; VDD=10 V; Tamb=25℃ 7
LOW-level output current IOL 3.4 6.8 mA VO=1.5 V; VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
HIGH-level output current IOH -0.51 -1 mA VO=4.6 V; VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
HIGH-level output current IOH -1.6 -3.2 mA VO=2.5 V; VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
HIGH-level output current IOH -1.3 -2.6 mA VO=9.5 V; VIN=0, 10 V; VDD=10 V; Tamb=25℃ 7
HIGH-level output current IOH -3.4 -6.8 mA VO=13.5 V; VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
LOW-level output voltage VOL 0 0.05 V VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
HIGH-level output voltage VOH 4.95 5 V VIN=0, 5 V; VDD=5 V; Tamb=25℃ 7
HIGH-level output voltage VOH 9.95 10 V VIN=0, 10 V; VDD=10 V; Tamb=25℃ 7
HIGH-level output voltage VOH 14.95 15 V VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
LOW-level input voltage VIL 1.5 V VO=0.5, 4.5 V; VDD=5 V; Tamb=25℃ 7
LOW-level input voltage VIL 3 V VO=1, 9 V; VDD=10 V; Tamb=25℃ 7
LOW-level input voltage VIL 4 V VO=1.5, 13.5 V; VDD=15 V; Tamb=25℃ 7
HIGH-level input voltage VIH 3.5 V VO=0.5, 4.5 V; VDD=5 V; Tamb=25℃ 7
HIGH-level input voltage VIH 7 V VO=1, 9 V; VDD=10 V; Tamb=25℃ 7
HIGH-level input voltage VIH 11 V VO=1.5, 13.5 V; VDD=15 V; Tamb=25℃ 7
input leakage current II -0.1 0.1 uA VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
OFF-state output current IOZ -0.4 0.4 uA VO=0, 15 V; VIN=0, 15 V; VDD=15 V; Tamb=25℃ 7
supply current IDD 5 uA VIN=0, 5 V; VDD=5 V; Tamb=-40℃ 8
supply current IDD 10 uA VIN=0, 10 V; VDD=10 V; Tamb=-40℃ 8
supply current IDD 20 uA VIN=0, 15 V; VDD=15 V; Tamb=-40℃ 8
supply current IDD 150 uA VIN=0, 5 V; VDD=5 V; Tamb=+85℃ 8
supply current IDD 300 uA VIN=0, 10 V; VDD=10 V; Tamb=+85℃ 8
supply current IDD 600 uA VIN=0, 15 V; VDD=15 V; Tamb=+85℃ 8
propagation delay time CP to QPn tPHL, tPLH 420 840 ns CP to QPn; see Figure 6; VDD=5V; Tamb=25℃ 9
propagation delay time CP to QPn tPHL, tPLH 195 390 ns CP to QPn; see Figure 6; VDD=10V; Tamb=25℃ 9
propagation delay time CP to QPn tPHL, tPLH 135 270 ns CP to QPn; see Figure 6; VDD=15V; Tamb=25℃ 9
input capacitance CI 5 7.5 pF any input; Tamb=25℃ 9

CAD (KiCad official)

  • Symbol: CD4094BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4094bm-etched.step / cd4094bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4094bm.step / cd4094bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 e32d07b3cc941eb5, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF