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CD4094BDTR
Public Made by Adomby adom
XBLW Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4094BDTR
XBLW · Shift Registers · SOP-16
CD4094BDTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input; data in each shift register stage is transferred to the storage register when STR is HIGH. |
| 2 | D | input | Serial data input to the 8-stage shift register. |
| 3 | CP | input | Clock input; data is shifted on positive-going clock transitions. |
| 4 | QP0 | tri_state | Parallel buffered 3-state output 0; data appears when OE is HIGH. |
| 5 | QP1 | tri_state | Parallel buffered 3-state output 1; data appears when OE is HIGH. |
| 6 | QP2 | tri_state | Parallel buffered 3-state output 2; data appears when OE is HIGH. |
| 7 | QP3 | tri_state | Parallel buffered 3-state output 3; data appears when OE is HIGH. |
| 8 | VSS | power_in | Ground (0V) reference for the supply. |
| 9 | QS1 | output | Serial output, updated on positive-going clock edges for cascading at high speed with fast clock rise time. |
| 10 | QS2 | output | Serial output, same data as QS1 on the next negative-going clock edge, for cascading with slow clock rise time. |
| 11 | QP7 | tri_state | Parallel buffered 3-state output 7; data appears when OE is HIGH. |
| 12 | QP6 | tri_state | Parallel buffered 3-state output 6; data appears when OE is HIGH. |
| 13 | QP5 | tri_state | Parallel buffered 3-state output 5; data appears when OE is HIGH. |
| 14 | QP4 | tri_state | Parallel buffered 3-state output 4; data appears when OE is HIGH. |
| 15 | OE | input | Output enable input; storage register data appears at the outputs when OE is HIGH. |
| 16 | VDD | power_in | Supply voltage, recommended range 3V to 15V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4094BDTR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4094bdtr-etched.step/cd4094bdtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4094bdtr.step/cd4094bdtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (18 pp, sha256
75aa29a6cb66a2ea, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).