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CD4094BD

Public Made by Adom

by adom

Sungine Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4094BD

Sungine · Shift Registers · DIP-16

CD4094BD from Sungine, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STROBE input Strobe input: when low the storage latches hold their data, and when high data passes from the shift register through the latches to the 3-state output buffers.
2 DATA input Serial data input to the 8-stage shift register.
3 CLOCK input Clock input to the 8-stage shift register.
4 Q1 tri_state Parallel 3-state output 1 of the storage register, enabled when OUTPUT ENABLE is high.
5 Q2 tri_state Parallel 3-state output 2 of the storage register, enabled when OUTPUT ENABLE is high.
6 Q3 tri_state Parallel 3-state output 3 of the storage register, enabled when OUTPUT ENABLE is high.
7 Q4 tri_state Parallel 3-state output 4 of the storage register, enabled when OUTPUT ENABLE is high.
8 VSS power_in Ground (VSS = 0 V reference).
9 QS output Serial output from the last stage of the 8-stage shift register.
10 Q'S output Second serial output of the shift register (Q'S).
11 Q8 tri_state Parallel 3-state output 8 of the storage register, enabled when OUTPUT ENABLE is high.
12 Q7 tri_state Parallel 3-state output 7 of the storage register, enabled when OUTPUT ENABLE is high.
13 Q6 tri_state Parallel 3-state output 6 of the storage register, enabled when OUTPUT ENABLE is high.
14 Q5 tri_state Parallel 3-state output 5 of the storage register, enabled when OUTPUT ENABLE is high.
15 OUTPUT ENABLE input When high, latched data is passed to the parallel outputs Q1-Q8; when low the outputs are high impedance.
16 VDD power_in Positive supply, recommended 3.0 to 15 V, absolute maximum -0.5 to 18 V.

Key specifications

Parameter Value
Manufacturer Sungine
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 4
Input voltage Vin -0.5 V -0.5 to VDD+0.5 4
Storage temperature Ts -65 150 °C 4
Power dissipation (DIP) PD 700 mW 双列直插式 (DIP) 4
Soldering temperature 260 °C 10 s 4
DC supply voltage VDD 3 15 V 4
Input voltage Vin 0 V 0 to VDD 4
Operating temperature -40 85 °C 4
Quiescent device current IDD 20 µA VDD=5V, 25°C 5
Quiescent device current IDD 40 µA VDD=10V, 25°C 5
Quiescent device current IDD 80 µA VDD=15V, 25°C 5
Low-level output voltage VOL 0 0.05 V VDD=5V, /IO/<1µA, 25°C 5
High-level output voltage VOH 4.95 5 V VDD=5V, /IO/<1µA, 25°C 5
High-level output voltage VOH 9.95 10 V VDD=10V, /IO/<1µA, 25°C 5
High-level output voltage VOH 14.95 15 V VDD=15V, /IO/<1µA, 25°C 5
Low-level input voltage VIL 1.5 V VDD=5V, Vo=0.5V or 4.5V 5
Low-level input voltage VIL 3 V VDD=10V, Vo=1.0V or 9V 5
Low-level input voltage VIL 4 V VDD=15V, VO=1.5V or 13.5V 5
High-level input voltage VIH 3.5 V VDD=5V, Vo=0.5V or 4.5V 5
High-level input voltage VIH 7 V VDD=10V, Vo=1.0V or 9.0V 5
High-level input voltage VIH 11 V VDD=15V, Vo=1.5V or 13.5V 5
Low-level output current IOL 0.44 0.88 mA VDD=5V, Vo=0.4V, 25°C 5
Low-level output current IOL 1.1 2.25 mA VDD=10V, Vo=0.5V, 25°C 5
Low-level output current IOL 3 8.8 mA VDD=15V, Vo=1.5V, 25°C 5
High-level output current IOH -0.44 mA VDD=5V, Vo=4.6V, 25°C 5
High-level output current IOH -1.1 mA VDD=10V, Vo=9.5V, 25°C 5
High-level output current IOH -3 mA VDD=15V, Vo=13.5V, 25°C 5
Input current IIN -0.3 0.3 µA VDD=15V, Vin=0V or 15V, 25°C 5
3-state output leakage current IOZ 1 µA VDD=15V, Vin=0V or 15V, 25°C 5
Propagation delay, clock to parallel output tPHL,tPLH 420 840 nS VDD=5V, TA=25°C, CL=50pF 6
Propagation delay, clock to parallel output tPHL,tPLH 195 390 nS VDD=10V, TA=25°C, CL=50pF 6
Propagation delay, clock to parallel output tPHL,tPLH 135 270 nS VDD=15V, TA=25°C, CL=50pF 6
Maximum clock frequency fmax 1.5 3 MHZ VDD=5V, TA=25°C, CL=50pF 7
Maximum clock frequency fmax 3 6 MHZ VDD=10V, TA=25°C, CL=50pF 7
Maximum clock frequency fmax 4 8 MHZ VDD=15V, TA=25°C, CL=50pF 7
Input capacitance Cin 5 7.5 pF 任意输入 (any input) 7

CAD (KiCad official)

  • Symbol: CD4094BD
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4094bd-etched.step / cd4094bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4094bd.step / cd4094bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (9 pp, sha256 3ec917946b0ead61, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF