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CD4093SA.TR

Wuxi I-core Elec · Gates · SOP-14

CD4093SA.TR from Wuxi I-core Elec, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of Schmitt NAND gate 1; unused inputs must be connected to VDD, VSS or another input.
2 1B input Data input 1B of Schmitt NAND gate 1; unused inputs must be connected to VDD, VSS or another input.
3 1Y output Data output 1Y of NAND gate 1, logic Y = NOT(A AND B) with standard symmetrical output characteristics.
4 2Y output Data output 2Y of NAND gate 2, logic Y = NOT(A AND B) with standard symmetrical output characteristics.
5 2A input Data input 2A of Schmitt NAND gate 2; unused inputs must be connected to VDD, VSS or another input.
6 2B input Data input 2B of Schmitt NAND gate 2; unused inputs must be connected to VDD, VSS or another input.
7 VSS power_in Ground reference, 0V, to which all voltages in the electrical characteristics are referenced.
8 3A input Data input 3A of Schmitt NAND gate 3; unused inputs must be connected to VDD, VSS or another input.
9 3B input Data input 3B of Schmitt NAND gate 3; unused inputs must be connected to VDD, VSS or another input.
10 3Y output Data output 3Y of NAND gate 3, logic Y = NOT(A AND B) with standard symmetrical output characteristics.
11 4Y output Data output 4Y of NAND gate 4, logic Y = NOT(A AND B) with standard symmetrical output characteristics.
12 4A input Data input 4A of Schmitt NAND gate 4; unused inputs must be connected to VDD, VSS or another input.
13 4B input Data input 4B of Schmitt NAND gate 4; unused inputs must be connected to VDD, VSS or another input.
14 VDD power_in Supply voltage, recommended range 3V to 15V with respect to VSS.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package SOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 5
DC input current IIK -10 10 mA any one input 5
Input voltage VI -0.5 V all inputs; max printed as VDD+0.5 5
Storage temperature Tstg -65 150 ℃ 5
Total power dissipation Ptot 500 mW 5
Device power per output transistor P 100 mW each output transistor 5
Soldering temperature TL 250 ℃ 10 s, SOP 5
Supply voltage VDD 3 15 V 6
Operating ambient temperature Tamb -40 85 ℃ free air 6
Quiescent current IDD 0.02 1 uA Tamb=25℃, VIN 0/5V, VDD=5V 6
Quiescent current IDD 0.02 2 uA Tamb=25℃, VIN 0/10V, VDD=10V 6
Quiescent current IDD 0.02 4 uA Tamb=25℃, VIN 0/15V, VDD=15V 6
Low-level output current IOL 0.51 1 mA Tamb=25℃, VO=0.4V, VIN 0/5V, VDD=5V 6
Low-level output current IOL 1.3 2.6 mA Tamb=25℃, VO=0.5V, VIN 0/10V, VDD=10V 6
Low-level output current IOL 3.4 6.8 mA Tamb=25℃, VO=1.5V, VIN 0/15V, VDD=15V 6
High-level output current IOH -0.51 -1 mA Tamb=25℃, VO=4.6V, VIN 0/5V, VDD=5V 6
High-level output current IOH -1.6 -3.2 mA Tamb=25℃, VO=2.5V, VIN 0/5V, VDD=5V 6
High-level output current IOH -1.3 -2.6 mA Tamb=25℃, VO=9.5V, VIN 0/10V, VDD=10V 6
High-level output current IOH -3.4 -6.8 mA Tamb=25℃, VO=13.5V, VIN 0/15V, VDD=15V 6
Low-level output voltage VOL 0 0.05 V Tamb=25℃, VIN 0/5V, VDD=5V 6
High-level output voltage VOH 4.95 5 V Tamb=25℃, VIN 0/5V, VDD=5V 6
High-level output voltage VOH 9.95 10 V Tamb=25℃, VIN 0/10V, VDD=10V 6
High-level output voltage VOH 14.95 15 V Tamb=25℃, VIN 0/15V, VDD=15V 6
Input leakage current II -0.1 0.1 uA Tamb=25℃, VIN 0/15V, VDD=15V 6
Positive threshold voltage VT+ 2.2 2.9 3.6 V Tamb=25℃, note [1], VDD=5V 7
Positive threshold voltage VT+ 4.6 5.9 7.1 V Tamb=25℃, note [1], VDD=10V 7
Positive threshold voltage VT+ 6.8 8.8 10.8 V Tamb=25℃, note [1], VDD=15V 7
Positive threshold voltage VT+ 2.6 3.3 4 V Tamb=25℃, note [2], VDD=5V 7
Positive threshold voltage VT+ 5.6 7 8.2 V Tamb=25℃, note [2], VDD=10V 7
Positive threshold voltage VT+ 6.3 9.4 12.7 V Tamb=25℃, note [2], VDD=15V 7
Negative threshold voltage VT- 0.9 1.9 2.8 V Tamb=25℃, note [1], VDD=5V 7
Negative threshold voltage VT- 2.5 3.9 5.2 V Tamb=25℃, note [1], VDD=10V 7
Negative threshold voltage VT- 4 5.8 7.4 V Tamb=25℃, note [1], VDD=15V 7
Negative threshold voltage VT- 1.4 2.3 3.2 V Tamb=25℃, note [2], VDD=5V 7
Negative threshold voltage VT- 3.4 5.1 6.6 V Tamb=25℃, note [2], VDD=10V 7
Negative threshold voltage VT- 4.8 7.3 9.6 V Tamb=25℃, note [2], VDD=15V 7
Hysteresis voltage VH 0.3 0.9 1.6 V Tamb=25℃, note [1], VDD=5V 7
Hysteresis voltage VH 1.2 2.3 3.4 V Tamb=25℃, note [1], VDD=10V 7
Hysteresis voltage VH 1.6 3.5 5 V Tamb=25℃, note [1], VDD=15V 7
Propagation delay tPHL, tPLH tPHL, tPLH 190 380 ns VDD=5V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Propagation delay tPHL, tPLH tPHL, tPLH 90 180 ns VDD=10V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Propagation delay tPHL, tPLH tPHL, tPLH 65 130 ns VDD=15V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Transition time tTHL, tTLH tTHL, tTLH 100 200 ns VDD=5V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Transition time tTHL, tTLH tTHL, tTLH 50 100 ns VDD=10V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Transition time tTHL, tTLH tTHL, tTLH 40 80 ns VDD=15V, tr,tf=20ns, CL=50pF, RL=200kΩ 7
Input capacitance CI 5 7.5 pF any input 7
Quiescent current at -40℃ IDD 1 uA Tamb=-40℃, VIN 0/5V, VDD=5V 6
Quiescent current at +85℃ IDD 30 uA Tamb=+85℃, VIN 0/5V, VDD=5V 6
Quiescent current at -40℃ IDD 2 uA Tamb=-40℃, VIN 0/10V, VDD=10V 6
Quiescent current at +85℃ IDD 60 uA Tamb=+85℃, VIN 0/10V, VDD=10V 6
Quiescent current at -40℃ IDD 4 uA Tamb=-40℃, VIN 0/15V, VDD=15V 6
Quiescent current at +85℃ IDD 120 uA Tamb=+85℃, VIN 0/15V, VDD=15V 6
Input leakage current at -40℃ II -0.1 0.1 uA Tamb=-40℃, VIN 0/15V, VDD=15V 7
Input leakage current at +85℃ II -1 1 uA Tamb=+85℃, VIN 0/15V, VDD=15V 7

CAD (KiCad official)

  • Symbol: CD4093SA.TR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4093sa-tr-etched.step / cd4093sa-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4093sa-tr.step / cd4093sa-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (14 pp, sha256 4b216317f190d49c, retrieved 2026-11-02, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF