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CD4093BP

Public Made by Adom

by adom

Sungine Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4093BP

Sungine · Logic Gates · SOP-14

CD4093BP from Sungine, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1A input Gate A input 1 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
2 IN2A input Gate A input 2 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
3 OUTA output Gate A NAND output; output current limited to ±10 mA absolute maximum.
4 OUTB output Gate B NAND output; output current limited to ±10 mA absolute maximum.
5 IN1B input Gate B input 1 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
6 IN2B input Gate B input 2 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
7 VSS power_in Ground (negative supply) pin.
8 IN1C input Gate C input 1 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
9 IN2C input Gate C input 2 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
10 OUTC output Gate C NAND output; output current limited to ±10 mA absolute maximum.
11 OUTD output Gate D NAND output; output current limited to ±10 mA absolute maximum.
12 IN1D input Gate D input 1 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
13 IN2D input Gate D input 2 with Schmitt trigger; input range -0.5 V to VDD+0.5 V.
14 VDD power_in Positive supply pin; operating range 3 to 18 V, absolute maximum -0.5 to +18 V.

Key specifications

Parameter Value
Manufacturer Sungine
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VDD -0.5 18 V 2
Input/output voltage range VIN, VOUT -0.5 V upper limit VDD+0.5 V 2
Input or output current IIN, IOUT -10 10 mA ±10 mA 2
Maximum power dissipation PD 500 mW 2
Storage temperature range Tstg -65 150 ℃ 2
Soldering temperature TL 260 ℃ 2
Operating ambient temperature TA 0 70 ℃ CD4093B 2
Operating supply voltage VDD 3 18 V wide operating voltage range 3~18V 1
Quiescent current IDD 0.0005 0.25 uA VIN=VDD or VSS, VDD=5V, 25℃ 3
Quiescent current IDD 0.001 0.5 uA VIN=VDD or VSS, VDD=10V, 25℃ 3
Quiescent current IDD 0.0015 1 uA VIN=VDD or VSS, VDD=15V, 25℃ 3
Output low voltage VOL 0 0.05 V VIN=VDD, VDD=5V, 25℃ 3
Output high voltage VOH 4.95 5 V VIN=VSS, VDD=5V, 25℃ 3
Output high voltage VOH 9.95 10 V VIN=VSS, VDD=10V, 25℃ 3
Output high voltage VOH 14.95 15 V VIN=VSS, VDD=15V, 25℃ 3
Output low current IOL 0.51 0.88 mA VOL=0.4, VDD=5V, 25℃ 3
Output low current IOL 1.3 2.25 mA VOL=0.5V, VDD=10V, 25℃ 3
Output low current IOL 3.4 8.8 mA VOL=1.5V, VDD=15V, 25℃ 3
Output high current IOH -2.4 -4.2 mA VOH=2.5V, VDD=5V, 25℃ 3
Output high current IOH -0.51 -0.88 mA VOH=4.6V, VDD=5V, 25℃ 3
Output high current IOH -1.3 -2.25 mA VOH=9.5V, VDD=10V, 25℃ 3
Output high current IOH -3.4 -8.8 mA VOH=13.5V, VDD=15V, 25℃ 3
Input capacitance CIN 5 7.5 pF VIN=0 3
Positive threshold voltage VT+ 2.2 2.9 3.6 V VDD=5V, 25℃ 3
Positive threshold voltage VT+ 4.6 5.9 7.1 V VDD=10V, 25℃ 3
Positive threshold voltage VT+ 6.8 8.8 10.8 V VDD=15V, 25℃ 3
Negative threshold voltage VT- 0.9 1.9 2.8 V VDD=5V, 25℃ 3
Negative threshold voltage VT- 2.5 3.9 5.2 V VDD=10V, 25℃ 3
Negative threshold voltage VT- 4 5.8 7.4 V VDD=15V, 25℃ 3
Hysteresis voltage VH 0.3 1.1 2 V VDD=5V, 25℃ 3
Hysteresis voltage VH 1.2 1.7 3.4 V VDD=10V, 25℃ 3
Hysteresis voltage VH 1.6 2.1 5 V VDD=15V, 25℃ 3
Output rise time tTLH 100 200 ns CL=50pF, TA=25℃, VDD=5V 4
Output rise time tTLH 50 100 ns CL=50pF, TA=25℃, VDD=10V 4
Output rise time tTLH 40 80 ns CL=50pF, TA=25℃, VDD=15V 4
Output fall time tTHL 100 200 ns CL=50pF, TA=25℃, VDD=5V 4
Output fall time tTHL 50 100 ns CL=50pF, TA=25℃, VDD=10V 4
Output fall time tTHL 40 80 ns CL=50pF, TA=25℃, VDD=15V 4
Propagation delay time tPLH, tPHL 125 250 ns CL=50pF, TA=25℃, VDD=5V 4
Propagation delay time tPLH, tPHL 50 100 ns CL=50pF, TA=25℃, VDD=10V 4
Propagation delay time tPLH, tPHL 40 80 ns CL=50pF, TA=25℃, VDD=15V 4

CAD (KiCad official)

  • Symbol: CD4093BP
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4093bp-etched.step / cd4093bp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4093bp.step / cd4093bp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (6 pp, sha256 8539024a59e948b0, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF