CD4093BM

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4093bm",
  "title": "CD4093BM",
  "brief": "JSMSEMI Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4093bm"
  ],
  "component": {
    "mpn": "CD4093BM",
    "manufacturer": "JSMSEMI",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309211039_JSMSEMI-CD4093BM_C5456626.pdf",
    "parts": {
      "symbol": "cd4093bm.kicad_sym",
      "footprint": "cd4093bm.kicad_mod",
      "model_3d": "cd4093bm-etched.glb",
      "model_3d_plain": "cd4093bm.glb",
      "model_3d_step": "cd4093bm-etched.step",
      "model_3d_step_plain": "cd4093bm.step",
      "lbr": "cd4093bm.lbr"
    },
    "distributor_links": {
      "lcsc": "C5456626"
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Gate 1 input A. Schmitt-trigger input of the first 2-input NAND gate. Typical VP=3.2 V and VN=1.8 V at VDD=5 V (hysteresis ~1.4 V)."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Gate 1 input B. Schmitt-trigger input of the first 2-input NAND gate. NAND output J = NOT(A AND B)."
      },
      {
        "number": "3",
        "name": "J",
        "type": "output",
        "description": "Gate 1 NAND output (J = NOT(A·B)). CMOS push-pull output, IOH ~ -1.8 mA at VDD=5 V; IOL ~ 3.6 mA at VDD=5 V."
      },
      {
        "number": "4",
        "name": "K",
        "type": "output",
        "description": "Gate 2 NAND output (K = NOT(C·D)). CMOS push-pull output driven by Schmitt-trigger inputs C and D."
      },
      {
        "number": "5",
        "name": "C",
        "type": "input",
        "description": "Gate 2 input C. Schmitt-trigger input of the second 2-input NAND gate; pairs with input D to drive output K."
      },
      {
        "number": "6",
        "name": "D",
        "type": "input",
        "description": "Gate 2 input D. Schmitt-trigger input of the second 2-input NAND gate; pairs with input C to drive output K."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference (0 V). Absolute maximum VDD-VSS is 20 V; recommended operating range 3.0 V to 15 V (up to 18 V absolute max)."
      },
      {
        "number": "8",
        "name": "E",
        "type": "input",
        "description": "Gate 3 input E. Schmitt-trigger input of the third 2-input NAND gate; pairs with input F to drive output L."
      },
      {
        "number": "9",
        "name": "F",
        "type": "input",
        "description": "Gate 3 input F. Schmitt-trigger input of the third 2-input NAND gate; pairs with input E to drive output L."
      },
      {
        "number": "10",
        "name": "L",
        "type": "output",
        "description": "Gate 3 NAND output (L = NOT(E·F)). CMOS push-pull output driven by Schmitt-trigger inputs E and F."
      },
      {
        "number": "11",
        "name": "M",
        "type": "output",
        "description": "Gate 4 NAND output (M = NOT(G·H)). CMOS push-pull output driven by Schmitt-trigger inputs G and H."
      },
      {
        "number": "12",
        "name": "G",
        "type": "input",
        "description": "Gate 4 input G. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input H to drive output M."
      },
      {
        "number": "13",
        "name": "H",
        "type": "input",
        "description": "Gate 4 input H. Schmitt-trigger input of the fourth 2-input NAND gate; pairs with input G to drive output M."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended operating range 3.0 V to 15 V; absolute maximum 20 V (spec limit 18 V). Input leakage IIN ≤ 1.2 µA and quiescent IDD ≤ 1.2 µA at VDD=18 V, Ta=25 °C."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309211039_JSMSEMI-CD4093BM_C5456626.pdf",
        "pages": 5,
        "sha256": "cc5896d280d3cc68",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "CD4093",
      "logic_family": "CD4000",
      "function_code": "4093",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Schmitt Trigger",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4093bm.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4093bm-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "183ce115ddb319a2a703da65591145bf42d61b6d3a8ea85b7a78a31e0618bf89",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "JSMSEMI",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4093bm"
  ],
  "discovery_pitch": "CD4093BM (JSMSEMI) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4093bm.kicad_sym",
    "cd4093bm.kicad_mod",
    "cd4093bm.glb",
    "cd4093bm.step",
    "cd4093bm-etched.step",
    "cd4093bm.lbr",
    "docs/hero.png",
    "docs/cd4093bm-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CD4093BM/TR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4093BE",
      "kind": "unknown"
    }
  ],
  "updated_at": "2026-09-24T18:49:11.195Z"
}