Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CD4093BE

Texas Instruments · Gates · DIP-14

CD4093BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 Schmitt-trigger input A. Together with pin 2 (B), drives NAND gate 1 whose output appears on pin 3 (J = A·B). Hysteresis ~0.9 V @ 5 V, ~2.3 V @ 10 V. Input current ±0.1 uA max.
2 1B input Gate 1 Schmitt-trigger input B. Paired with pin 1 (A) to form NAND gate 1; output on pin 3.
3 1J output Gate 1 NAND output, J = NAND(A,B) (datasheet notation 'J = A·B' denoting the NAND). CMOS symmetrical output; IOL/IOH min 0.51 mA @ 5 V, 1.3 mA @ 10 V, 3.4 mA @ 15 V.
4 2K output Gate 2 NAND output, K = NAND(C,D). Symmetrical CMOS output drive.
5 2C input Gate 2 Schmitt-trigger input C. Paired with pin 6 (D) to drive NAND gate 2 whose output is pin 4 (K).
6 2D input Gate 2 Schmitt-trigger input D. Paired with pin 5 (C) for NAND gate 2.
7 VSS power_in Negative supply / ground reference. All voltages are referenced to VSS. Tie to 0 V for single-supply operation.
8 3E input Gate 3 Schmitt-trigger input E. Paired with pin 9 (F) to drive NAND gate 3 whose output is pin 10 (L).
9 3F input Gate 3 Schmitt-trigger input F. Paired with pin 8 (E) for NAND gate 3.
10 3L output Gate 3 NAND output, L = NAND(E,F). Symmetrical CMOS output drive.
11 4M output Gate 4 NAND output, M = NAND(G,H). Symmetrical CMOS output drive.
12 4G input Gate 4 Schmitt-trigger input G. Paired with pin 13 (H) to drive NAND gate 4 whose output is pin 11 (M).
13 4H input Gate 4 Schmitt-trigger input H. Paired with pin 12 (G) for NAND gate 4.
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V (absolute max −0.5 V to +20 V referenced to VSS). Quiescent supply current typ 0.02 uA at 25 °C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4093BEE
  • CD4093BEEE4
  • CD4093BEF3A
  • CD4093BEF
  • CD4093BEM
  • CD4093BEM96
  • CD4093BEMT
  • CD4093BEMG4
  • CD4093BEM96E4
  • CD4093BEM96G4
  • CD4093BENSR
  • CD4093BENSRG4
  • CD4093BEPW
  • CD4093BEPWR
  • CD4093BEPWG4
  • CD4093BEPWRG4

CAD (KiCad official)

  • Symbol: CD4093BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4093be-etched.step / cd4093be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4093be.step / cd4093be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 32271fec668a1702, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF