# CD4093BDRG

**HANSCHIP semiconductor** · Gates · SOP-14

CD4093BDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | NAND gate 1 input A. Schmitt-trigger input; logic-high threshold typ 2.9 V at VDD=5 V, 5.9 V at VDD=10 V, 8.8 V at VDD=15 V. |
| 2 | 1B | input | NAND gate 1 input B. Schmitt-trigger input; threshold differs slightly from the A input of the same gate. |
| 3 | 1Y | output | NAND gate 1 output. Y = NOT(A AND B). CMOS push-pull output, IOH/IOL ≈ 1 mA @ VDD=5 V, 6.8 mA @ VDD=15 V. |
| 4 | 2Y | output | NAND gate 2 output. Y = NOT(A AND B). CMOS push-pull output. |
| 5 | 2A | input | NAND gate 2 input A. Schmitt-trigger input. |
| 6 | 2B | input | NAND gate 2 input B. Schmitt-trigger input. |
| 7 | VSS | power_in | Negative supply / ground reference (0 V). |
| 8 | 3A | input | NAND gate 3 input A. Schmitt-trigger input. |
| 9 | 3B | input | NAND gate 3 input B. Schmitt-trigger input. |
| 10 | 3Y | output | NAND gate 3 output. Y = NOT(A AND B). CMOS push-pull output. |
| 11 | 4Y | output | NAND gate 4 output. Y = NOT(A AND B). CMOS push-pull output. |
| 12 | 4A | input | NAND gate 4 input A. Schmitt-trigger input. |
| 13 | 4B | input | NAND gate 4 input B. Schmitt-trigger input. |
| 14 | VDD | power_in | Positive supply. Recommended 3 V to 15 V; absolute max 18 V. Quiescent IDD typ 0.02 µA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## Ordering variants

Same part, different packaging or reel option.

- `CD4093BDRG`
- `CD4093BDRGPG`
- `CD4093BDRGPWRG`

## CAD (KiCad official)

- Symbol: `CD4093BDRG`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4093bdrg-etched.step` / `cd4093bdrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4093bdrg.step` / `cd4093bdrg.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`cd4093bdrg.step`](cd4093bdrg.step) | 195 KB | You want the bare part, or you mark your own boards. |
| [`cd4093bdrg-etched.step`](cd4093bdrg-etched.step) | 2.7 MB | You want the part with `CD4093BDRG` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 666 faces against 237 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HANSCHIP semiconductor datasheet](docs/cd4093bdrg-datasheet.pdf) (10 pp, sha256 `d7a40f9772ab7645`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4093bdrg-datasheet.pdf)