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CD4093AMS

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HGSEMI Logic Gates, QSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4093AMS

HGSEMI · Logic Gates · QSOP-16

CD4093AMS from HGSEMI, in a QSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of Schmitt-trigger NAND gate 1; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
2 1B input Data input B of Schmitt-trigger NAND gate 1; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
3 1Y output Data output of NAND gate 1 (Y = NOT(A AND B)).
4 2Y output Data output of NAND gate 2 (Y = NOT(A AND B)).
5 2A input Data input A of Schmitt-trigger NAND gate 2; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
6 2B input Data input B of Schmitt-trigger NAND gate 2; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
7 VSS power_in Ground reference, 0 V.
8 NC unconnected No internal connection.
9 NC unconnected No internal connection.
10 3A input Data input A of Schmitt-trigger NAND gate 3; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
11 3B input Data input B of Schmitt-trigger NAND gate 3; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
12 3Y output Data output of NAND gate 3 (Y = NOT(A AND B)).
13 4Y output Data output of NAND gate 4 (Y = NOT(A AND B)).
14 4A input Data input A of Schmitt-trigger NAND gate 4; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
15 4B input Data input B of Schmitt-trigger NAND gate 4; input voltage must stay within VSS to VDD and unused inputs must be tied to VDD, VSS or another input.
16 VDD power_in Supply voltage; recommended operating range 3 V to 15 V referenced to VSS, absolute maximum -0.5 V to 18 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package QSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (referenced to VSS) VDD -0.5 18 V Referenced to VSS pin 4
Input voltage (all inputs) VIN -0.5 V 4
Input current (any input) IIN -10 10 mA Any input 4
Operating temperature TA -40 85 ℃ 4
Maximum operating junction temperature TJ 150 ℃ 4
Storage temperature TS -65 150 ℃ 4
Soldering temperature TW 260 ℃ 10 s 4
Supply voltage VDD 3 15 V VSS=0 V, Tamb=25℃ unless otherwise specified 4
Input voltage VIN 0 V VSS=0 V, Tamb=25℃ unless otherwise specified 4
Quiescent current IDD 0 0.1 uA VI 0,5 V; VDD 5 V 5
Low-level output current IOL 1 1.9 mA VO 0.4 V; VI 0,5 V; VDD 5 V 5
Low-level output current IOL 2 5.5 mA VO 0.5 V; VI 0,10 V; VDD 10 V 5
Low-level output current IOL 10 22 mA VO 1.5 V; VI 0,15 V; VDD 15 V 5
High-level output current IOH -1 -2.4 mA VO 4.6 V; VI 0,5 V; VDD 5 V 5
High-level output current IOH -4 -9.2 mA VO 2.5 V; VI 0,5 V; VDD 5 V 5
High-level output current IOH -2 -5.2 mA VO 9.5 V; VI 0,10 V; VDD 10 V 5
High-level output current IOH -10 -20 mA VO 13.5 V; VI 0,15 V; VDD 15 V 5
Low-level output voltage VOL 0 0.05 V VI 0,5 V; VDD 5 V 5
High-level output voltage VOH 4.95 5 V VI 0,5 V; VDD 5 V 5
High-level output voltage VOH 9.95 10 V VI 0,10 V; VDD 10 V 5
High-level output voltage VOH 14.95 15 V VI 0,15 V; VDD 15 V 5
Input leakage current IIL -0.1 0.1 uA VI 0,15 V; VDD 15 V 5
Propagation delay (input to output) tPHL, tPLH 190 380 ns Ref. Fig. 2; VDD=5V 5
Propagation delay (input to output) tPHL, tPLH 90 180 ns Ref. Fig. 2; VDD=10V 5
Propagation delay (input to output) tPHL, tPLH 65 130 ns Ref. Fig. 2; VDD=15V 5
Output transition time tTHL, tTLH 100 200 ns Ref. Fig. 2; VDD=5V 5
Output transition time tTHL, tTLH 50 100 ns Ref. Fig. 2; VDD=10V 5
Output transition time tTHL, tTLH 40 80 ns Ref. Fig. 2; VDD=15V 5
Input capacitance CIN 5 7.5 pF Any input 5
Positive threshold voltage VT+ 3.3 3.5 3.7 V Note [1]; VDD=5 V 6
Positive threshold voltage VT+ 6.4 6.5 6.6 V Note [1]; VDD=10 V 6
Positive threshold voltage VT+ 9.3 9.4 9.5 V Note [1]; VDD=15 V 6
Negative threshold voltage VT- 1.6 1.7 1.8 V Note [1]; VDD=5 V 6
Negative threshold voltage VT- 3.6 3.7 3.8 V Note [1]; VDD=10 V 6
Negative threshold voltage VT- 5.5 5.6 5.7 V Note [1]; VDD=15 V 6
Hysteresis voltage VH 1.5 1.8 2.1 V Note [1]; VDD=5 V 6
Hysteresis voltage VH 2.6 2.8 3 V Note [1]; VDD=10 V 6
Hysteresis voltage VH 3.6 3.8 4 V Note [1]; VDD=15 V 6

CAD (KiCad official)

  • Symbol: CD4093AMS
  • Footprint: Package_SO:QSOP-16_3.9x4.9mm_P0.635mm
  • 3D model: QSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4093ams-etched.step / cd4093ams-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4093ams.step / cd4093ams.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (12 pp, sha256 70edda0a56934a14, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF