CD4085BPWR

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  "type": "component",
  "slug": "cd4085bpwr",
  "title": "CD4085BPWR",
  "brief": "Texas Instruments Logic Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "cd4085bpwr"
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  "component": {
    "mpn": "CD4085BPWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4085b.pdf",
    "parts": {
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      "lbr": "cd4085bpwr.lbr"
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    "pins": [
      {
        "number": "1",
        "name": "A1",
        "type": "input",
        "description": "Gate-1 A input. First input of the first 2-input AND gate feeding the gate-1 NOR/AOI network. CMOS logic input; VIH min = 3.5 V @ VDD = 5 V, 7 V @ 10 V, 11 V @ 15 V; input current typ ±1e-5 μA."
      },
      {
        "number": "2",
        "name": "B1",
        "type": "input",
        "description": "Gate-1 B input. Second input of the A1·B1 AND term feeding the gate-1 AOI network. Standard CMOS input, same DC characteristics as the other logic inputs."
      },
      {
        "number": "3",
        "name": "E1",
        "type": "output",
        "description": "Gate-1 AOI output. E1 = INHIBIT1 + A1·B1 + C1·D1 (active-high OR of the inhibit and the two AND terms, then inverted internally per B-series AOI convention). Standardized symmetrical CMOS output; IOL/IOH characterized at 5/10/15 V (e.g. IOL min 0.51 mA @ VDD=5 V, 1.3 mA @ 10 V, 3.4 mA @ 15 V)."
      },
      {
        "number": "4",
        "name": "E2",
        "type": "output",
        "description": "Gate-2 AOI output. E2 = INHIBIT2 + A2·B2 + C2·D2. Same drive characteristics as E1."
      },
      {
        "number": "5",
        "name": "A2",
        "type": "input",
        "description": "Gate-2 A input. First input of the A2·B2 AND term feeding the gate-2 AOI network."
      },
      {
        "number": "6",
        "name": "B2",
        "type": "input",
        "description": "Gate-2 B input. Second input of the A2·B2 AND term feeding the gate-2 AOI network."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference for the device. Tie to 0 V. Datasheet notes TERM.7 = VSS."
      },
      {
        "number": "8",
        "name": "C2",
        "type": "input",
        "description": "Gate-2 C input. First input of the C2·D2 AND term feeding the gate-2 AOI network."
      },
      {
        "number": "9",
        "name": "D2",
        "type": "input",
        "description": "Gate-2 D input. Second input of the C2·D2 AND term feeding the gate-2 AOI network."
      },
      {
        "number": "10",
        "name": "INHIBIT1",
        "type": "input",
        "description": "Gate-1 inhibit input. Active-high term inside the AOI expression E1 = INHIBIT1 + A1·B1 + C1·D1; forcing INHIBIT1 high forces E1 to the OR-then-inverted output state regardless of the AND terms. Individually controls gate 1 (allows use of the two AND gates and NOR gate independently, per the datasheet features list)."
      },
      {
        "number": "11",
        "name": "INHIBIT2",
        "type": "input",
        "description": "Gate-2 inhibit input. Same function as INHIBIT1 but for gate 2; drives the OR term inside E2 = INHIBIT2 + A2·B2 + C2·D2."
      },
      {
        "number": "12",
        "name": "C1",
        "type": "input",
        "description": "Gate-1 C input. First input of the C1·D1 AND term feeding the gate-1 AOI network."
      },
      {
        "number": "13",
        "name": "D1",
        "type": "input",
        "description": "Gate-1 D input. Second input of the C1·D1 AND term feeding the gate-1 AOI network."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended operating range 3 V to 18 V; absolute maximum -0.5 V to +20 V referenced to VSS. Datasheet notes TERM.14 = VDD."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4085b.pdf",
        "pages": null,
        "sha256": "0169c8587f0ccebf",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
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    "logic": {
      "family_id": "CD4085",
      "logic_family": "CD4000",
      "function_code": "4085",
      "function_class": "Gate",
      "function_name": "Dual 2-Wide 2-Input AND-OR-INVERT Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "checked": "2026-10-19",
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      }
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  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "TSSOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "CD4085BPWR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRE",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRF",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRF3A",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRM",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRMT",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRM96",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BPWRNSR",
      "kind": "packaging"
    }
  ],
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  "discovery_pitch": "CD4085BPWR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
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  "visibility": {
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  "updated_at": "2026-09-24T18:48:38.330Z"
}