# CD4085BPWR

**Texas Instruments** · Logic Gates · TSSOP-14

CD4085BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Gate-1 A input. First input of the first 2-input AND gate feeding the gate-1 NOR/AOI network. CMOS logic input; VIH min = 3.5 V @ VDD = 5 V, 7 V @ 10 V, 11 V @ 15 V; input current typ ±1e-5 μA. |
| 2 | B1 | input | Gate-1 B input. Second input of the A1·B1 AND term feeding the gate-1 AOI network. Standard CMOS input, same DC characteristics as the other logic inputs. |
| 3 | E1 | output | Gate-1 AOI output. E1 = INHIBIT1 + A1·B1 + C1·D1 (active-high OR of the inhibit and the two AND terms, then inverted internally per B-series AOI convention). Standardized symmetrical CMOS output; IOL/IOH characterized at 5/10/15 V (e.g. IOL min 0.51 mA @ VDD=5 V, 1.3 mA @ 10 V, 3.4 mA @ 15 V). |
| 4 | E2 | output | Gate-2 AOI output. E2 = INHIBIT2 + A2·B2 + C2·D2. Same drive characteristics as E1. |
| 5 | A2 | input | Gate-2 A input. First input of the A2·B2 AND term feeding the gate-2 AOI network. |
| 6 | B2 | input | Gate-2 B input. Second input of the A2·B2 AND term feeding the gate-2 AOI network. |
| 7 | VSS | power_in | Negative supply / ground reference for the device. Tie to 0 V. Datasheet notes TERM.7 = VSS. |
| 8 | C2 | input | Gate-2 C input. First input of the C2·D2 AND term feeding the gate-2 AOI network. |
| 9 | D2 | input | Gate-2 D input. Second input of the C2·D2 AND term feeding the gate-2 AOI network. |
| 10 | INHIBIT1 | input | Gate-1 inhibit input. Active-high term inside the AOI expression E1 = INHIBIT1 + A1·B1 + C1·D1; forcing INHIBIT1 high forces E1 to the OR-then-inverted output state regardless of the AND terms. Individually controls gate 1 (allows use of the two AND gates and NOR gate independently, per the datasheet features list). |
| 11 | INHIBIT2 | input | Gate-2 inhibit input. Same function as INHIBIT1 but for gate 2; drives the OR term inside E2 = INHIBIT2 + A2·B2 + C2·D2. |
| 12 | C1 | input | Gate-1 C input. First input of the C1·D1 AND term feeding the gate-1 AOI network. |
| 13 | D1 | input | Gate-1 D input. Second input of the C1·D1 AND term feeding the gate-1 AOI network. |
| 14 | VDD | power_in | Positive supply. Recommended operating range 3 V to 18 V; absolute maximum -0.5 V to +20 V referenced to VSS. Datasheet notes TERM.14 = VDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Ordering variants

Same part, different packaging or reel option.

- `CD4085BPWR`
- `CD4085BPWRE`
- `CD4085BPWRF`
- `CD4085BPWRF3A`
- `CD4085BPWRM`
- `CD4085BPWRMT`
- `CD4085BPWRM96`
- `CD4085BPWRNSR`

## CAD (KiCad official)

- Symbol: `CD4085BPWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4085bpwr-etched.step` / `cd4085bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4085bpwr.step` / `cd4085bpwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4085b.pdf) (None pp, sha256 `0169c8587f0ccebf`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4085bpwr-datasheet.pdf)