CD4085BM

{
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  "type": "component",
  "slug": "cd4085bm",
  "title": "CD4085BM",
  "brief": "Texas Instruments Logic Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4085bm"
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  "component": {
    "mpn": "CD4085BM",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4085b",
    "parts": {
      "symbol": "cd4085bm.kicad_sym",
      "footprint": "cd4085bm.kicad_mod",
      "model_3d": "cd4085bm-etched.glb",
      "model_3d_plain": "cd4085bm.glb",
      "model_3d_step": "cd4085bm-etched.step",
      "model_3d_step_plain": "cd4085bm.step",
      "lbr": "cd4085bm.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "A1",
        "type": "input",
        "description": "Data input A of the first AND gate in AOI gate 1. Combined with B1 into the first 2-input AND of AOI 1. CMOS logic input (VIL max 1.5/3/4 V and VIH min 3.5/7/11 V at VDD = 5/10/15 V)."
      },
      {
        "number": "2",
        "name": "B1",
        "type": "input",
        "description": "Data input B of the first AND gate in AOI gate 1. Combined with A1 into the first 2-input AND of AOI 1. CMOS logic input."
      },
      {
        "number": "3",
        "name": "E1",
        "type": "output",
        "description": "Output of AOI gate 1. Realizes E1 = INH1 + A1·B1 + C1·D1 (a 3-input NOR of INHIBIT1 with the two AND products A1·B1 and C1·D1). Standardized symmetrical CMOS output."
      },
      {
        "number": "4",
        "name": "E2",
        "type": "output",
        "description": "Output of AOI gate 2. Realizes E2 = INH2 + A2·B2 + C2·D2 (3-input NOR of INHIBIT2 with the two AND products A2·B2 and C2·D2). Standardized symmetrical CMOS output."
      },
      {
        "number": "5",
        "name": "A2",
        "type": "input",
        "description": "Data input A of the first AND gate in AOI gate 2. Combined with B2 into the first 2-input AND of AOI 2. CMOS logic input."
      },
      {
        "number": "6",
        "name": "B2",
        "type": "input",
        "description": "Data input B of the first AND gate in AOI gate 2. Combined with A2 into the first 2-input AND of AOI 2. CMOS logic input."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference for the device. Absolute maximum input voltage referenced to VSS is -0.5 V to VDD+0.5 V."
      },
      {
        "number": "8",
        "name": "C2",
        "type": "input",
        "description": "Data input C of the second AND gate in AOI gate 2. Combined with D2 into the second 2-input AND of AOI 2. CMOS logic input."
      },
      {
        "number": "9",
        "name": "D2",
        "type": "input",
        "description": "Data input D of the second AND gate in AOI gate 2. Combined with C2 into the second 2-input AND of AOI 2. CMOS logic input."
      },
      {
        "number": "10",
        "name": "INHIBIT1",
        "type": "input",
        "description": "Inhibit control for AOI gate 1. When high, forces E1 low regardless of the A1/B1/C1/D1 inputs (INH1 appears in the NOR term of E1 = INH1 + A1·B1 + C1·D1). CMOS logic input."
      },
      {
        "number": "11",
        "name": "INHIBIT2",
        "type": "input",
        "description": "Inhibit control for AOI gate 2. When high, forces E2 low regardless of the A2/B2/C2/D2 inputs (INH2 appears in the NOR term of E2 = INH2 + A2·B2 + C2·D2). CMOS logic input."
      },
      {
        "number": "12",
        "name": "C1",
        "type": "input",
        "description": "Data input C of the second AND gate in AOI gate 1. Combined with D1 into the second 2-input AND of AOI 1. CMOS logic input."
      },
      {
        "number": "13",
        "name": "D1",
        "type": "input",
        "description": "Data input D of the second AND gate in AOI gate 1. Combined with C1 into the second 2-input AND of AOI 1. CMOS logic input."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended supply-voltage range 3 V to 18 V; absolute maximum -0.5 V to 20 V. Parametric ratings characterized at 5 V, 10 V, and 15 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4085b",
        "pages": null,
        "sha256": "0169c8587f0ccebf",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4085",
      "logic_family": "CD4000",
      "function_code": "4085",
      "function_class": "Gate",
      "function_name": "Dual 2-Wide 2-Input AND-OR-INVERT Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
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        "checked": "2026-10-19",
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      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "CD4085BMM",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMMT",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMM96",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMNSR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BME",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMF",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMF3A",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMPW",
      "kind": "packaging"
    },
    {
      "mpn": "CD4085BMPWR",
      "kind": "packaging"
    }
  ],
  "sections": [
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    "viewers",
    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
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  "discovery_pitch": "CD4085BM (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "README.md",
    "cd4085bm.kicad_sym",
    "cd4085bm.kicad_mod",
    "cd4085bm.glb",
    "cd4085bm.step",
    "cd4085bm.lbr",
    "docs/hero.png",
    "docs/cd4085bm-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
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  },
  "updated_at": "2026-09-24T18:48:29.870Z"
}