component
CD4082NS14ARDQ
Public Made by Adomby adom
GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4082NS14ARDQ
GR · Logic Gates · SOP-14
CD4082NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output of gate 1; per the truth table it is high only when inputs 1A, 1B, 1C and 1D are all high. |
| 2 | 1A | input | Data input A of AND gate 1; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 3 | 1B | input | Data input B of AND gate 1; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 4 | 1C | input | Data input C of AND gate 1; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 5 | 1D | input | Data input D of AND gate 1; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 6 | NC | unconnected | Not connected; the datasheet lists this pin as NC with no function. |
| 7 | VSS | power_in | Ground reference; all datasheet voltages are referenced to VSS (0 V). |
| 8 | NC | unconnected | Not connected; the datasheet lists this pin as NC with no function. |
| 9 | 2A | input | Data input A of AND gate 2; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 10 | 2B | input | Data input B of AND gate 2; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 11 | 2C | input | Data input C of AND gate 2; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 12 | 2D | input | Data input D of AND gate 2; all inputs are limited to -0.5 V to VDD+0.5 V. |
| 13 | 2Y | output | Data output of gate 2; per the truth table it is high only when inputs 2A, 2B, 2C and 2D are all high. |
| 14 | VDD | power_in | Supply voltage, referenced to VSS; the absolute maximum DC supply range is -0.5 V to 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range (referenced to VSS terminals) | VDD | -0.5 | 20 | V | Voltage referenced to VSS terminals | 3 | |
| Input Voltage Range, All Inputs | VI | -0.5 | V | 3 | |||
| Power Dissipation | PD | 500 | mW | 3 | |||
| Junction Temperature | TJ | 125 | ℃ | 3 | |||
| Operating Temperature | TOP | -40 | 85 | ℃ | 3 | ||
| Supply Current | IDD | 0 | 1 | uA | Ta=25℃; VIN=0,5 V; VDD=5 V | 3 | |
| Low Level Output Current | IOL | 1.5 | 3 | mA | Ta=25℃; VO=0.4 V; VIN=0,5 V; VDD=5 V | 3 | |
| Low Level Output Current | IOL | 4 | 8 | mA | Ta=25℃; VO=0.5 V; VIN=0,10 V; VDD=10 V | 3 | |
| Low Level Output Current | IOL | 15 | 30 | mA | Ta=25℃; VO=1.5 V; VIN=0,15 V; VDD=15 V | 3 | |
| High Level Output Current | IOH | -0.5 | -2 | mA | Ta=25℃; VO=4.6 V; VIN=0,5 V; VDD=5 V | 3 | |
| High Level Output Current | IOH | -4 | -8 | mA | Ta=25℃; VO=2.5 V; VIN=0,5 V; VDD=5 V | 3 | |
| High Level Output Current | IOH | -2 | -4 | mA | Ta=25℃; VO=9.5 V; VIN=0,10 V; VDD=10 V | 3 | |
| High Level Output Current | IOH | -7 | -14 | mA | Ta=25℃; VO=13.5 V; VIN=0,15 V; VDD=15 V | 3 | |
| Low Level Output Voltage | VOL | 0 | 0.05 | V | Ta=25℃; VIN=0,5 V; VDD=5 V | 3 | |
| High Level Output Voltage | VOH | 4.95 | 5 | V | Ta=25℃; VIN=0,5 V; VDD=5 V | 3 | |
| High Level Output Voltage | VOH | 9.95 | 10 | V | Ta=25℃; VIN=0,10 V; VDD=10 V | 3 | |
| High Level Output Voltage | VOH | 14.95 | 15 | V | Ta=25℃; VIN=0,15 V; VDD=15 V | 3 | |
| Low Level Input Voltage | VIL | 1.5 | V | Ta=25℃; VO=0.5,4.5 V; VDD=5 V | 3 | ||
| Low Level Input Voltage | VIL | 3 | V | Ta=25℃; VO=1,9 V; VDD=10 V | 3 | ||
| Low Level Input Voltage | VIL | 4 | V | Ta=25℃; VO=1.5,13.5 V; VDD=15 V | 3 | ||
| High Level Input Voltage | VIH | 3.5 | V | Ta=25℃; VO=0.5,4.5 V; VDD=5 V | 3 | ||
| High Level Input Voltage | VIH | 7 | V | Ta=25℃; VO=1,9 V; VDD=10 V | 3 | ||
| High Level Input Voltage | VIH | 11 | V | Ta=25℃; VO=1.5,13.5 V; VDD=15 V | 3 | ||
| Input Leakage Current | IIN | -1 | 0 | 1 | uA | Ta=25℃; VIN=0,18 V; VDD=18 V | 3 |
CAD (KiCad official)
- Symbol:
CD4082NS14ARDQ - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4082ns14ardq-etched.step/cd4082ns14ardq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4082ns14ardq.step/cd4082ns14ardq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (7 pp, sha256
b3f1118134dcce48, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).