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CD4082BM96

Public Made by Adom

by adom

Texas Instruments Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cd4082bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cd4082bm96: viewers · Ray 2mo ago
cd4082bm96-etched.fit.json cd4082bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4082bm96-etched.glb cd4082bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
cd4082bm96-etched.step cd4082bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
cd4082bm96.glb Publish 0.1.0 · Ray 2mo ago
cd4082bm96.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4082bm96.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4082bm96.lbr Publish 0.1.0 · Ray 2mo ago
cd4082bm96.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
page.json cd4082bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
README.md cd4082bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4082BM96

Texas Instruments · Gates · SOIC-14

CD4082BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 J output Output of gate 1 (J = A AND B AND C AND D). CMOS push-pull output; typical VOH ≈ VDD and VOL ≈ VSS with symmetrical drive (see IOL/IOH tables).
2 D input Input D of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. VIL/VIH per B-series specs (e.g. VIL ≤ 1.5 V, VIH ≥ 3.5 V at VDD = 5 V).
3 C input Input C of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
4 B input Input B of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
5 A input Input A of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
6 NC unconnected No internal connection. Leave floating or tie to VDD/VSS on the PCB per designer preference.
7 VSS power_in Negative supply / ground reference (0 V). All input/output logic levels are referenced to VSS. Package power dissipation is 500 mW max.
8 E input Input E of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
9 NC unconnected No internal connection. Leave floating or tie to VDD/VSS on the PCB per designer preference.
10 F input Input F of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
11 G input Input G of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
12 H input Input H of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network.
13 K output Output of gate 2 (K = E AND F AND G AND H). CMOS push-pull output; typical VOH ≈ VDD and VOL ≈ VSS with symmetrical drive (see IOL/IOH tables).
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V; absolute max −0.5 V to +20 V referenced to VSS. Bypass with a local ceramic capacitor to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4082BM96
  • CD4082BM96E4
  • CD4082BM96G4
  • CD4082BM96BME4
  • CD4082BM96BMG4
  • CD4082BM96BMT
  • CD4082BM96BMTE4
  • CD4082BM96BMTG4
  • CD4082BM96BE
  • CD4082BM96BEE4
  • CD4082BM96BF
  • CD4082BM96BF3A
  • CD4082BM96BNSR
  • CD4082BM96BNSRE4
  • CD4082BM96BNSRG4
  • CD4082BM96BPW
  • CD4082BM96BPWE4
  • CD4082BM96BPWG4
  • CD4082BM96BPWR
  • CD4082BM96BPWRE4
  • CD4082BM96BPWRG4

CAD (KiCad official)

  • Symbol: CD4082BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4082bm96-etched.step / cd4082bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4082bm96.step / cd4082bm96.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4082bm96.step 195 KB You want the bare part, or you mark your own boards.
cd4082bm96-etched.step 2.8 MB You want the part with CD4082BM96 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 673 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 4c6b419a4c352c19, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF