CD4082BM96

@@ -0,0 +1,73 @@+# CD4082BM96++**Texas Instruments** · Gates · SOIC-14++CD4082BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | J | output | Output of gate 1 (J = A AND B AND C AND D). CMOS push-pull output; typical VOH ≈ VDD and VOL ≈ VSS with symmetrical drive (see IOL/IOH tables). |+| 2 | D | input | Input D of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. VIL/VIH per B-series specs (e.g. VIL ≤ 1.5 V, VIH ≥ 3.5 V at VDD = 5 V). |+| 3 | C | input | Input C of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 4 | B | input | Input B of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 5 | A | input | Input A of gate 1 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 6 | NC | unconnected | No internal connection. Leave floating or tie to VDD/VSS on the PCB per designer preference. |+| 7 | VSS | power_in | Negative supply / ground reference (0 V). All input/output logic levels are referenced to VSS. Package power dissipation is 500 mW max. |+| 8 | E | input | Input E of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 9 | NC | unconnected | No internal connection. Leave floating or tie to VDD/VSS on the PCB per designer preference. |+| 10 | F | input | Input F of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 11 | G | input | Input G of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 12 | H | input | Input H of gate 2 (4-input AND). CMOS logic input, protected by on-chip CMOS protection network. |+| 13 | K | output | Output of gate 2 (K = E AND F AND G AND H). CMOS push-pull output; typical VOH ≈ VDD and VOL ≈ VSS with symmetrical drive (see IOL/IOH tables). |+| 14 | VDD | power_in | Positive supply. Recommended operating range 3 V to 18 V; absolute max −0.5 V to +20 V referenced to VSS. Bypass with a local ceramic capacitor to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4082BM96`+- `CD4082BM96E4`+- `CD4082BM96G4`+- `CD4082BM96BME4`+- `CD4082BM96BMG4`+- `CD4082BM96BMT`+- `CD4082BM96BMTE4`+- `CD4082BM96BMTG4`+- `CD4082BM96BE`+- `CD4082BM96BEE4`+- `CD4082BM96BF`+- `CD4082BM96BF3A`+- `CD4082BM96BNSR`+- `CD4082BM96BNSRE4`+- `CD4082BM96BNSRG4`+- `CD4082BM96BPW`+- `CD4082BM96BPWE4`+- `CD4082BM96BPWG4`+- `CD4082BM96BPWR`+- `CD4082BM96BPWRE4`+- `CD4082BM96BPWRG4`++## CAD (KiCad official)++- Symbol: `CD4082BM96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4082bm96.pdf) (31 pp, sha256 `4c6b419a4c352c19`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4082bm96-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "cd4082bm96",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4082bm96"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4082bm96.kicad_sym",+    "cd4082bm96.kicad_mod",+    "cd4082bm96.glb",+    "cd4082bm96.step",+    "cd4082bm96.lbr",+    "docs/hero.png",+    "docs/cd4082bm96-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file