component

CD4082BM

Public Made by Adom

by adom

lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4082bmfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers cd4082bm: viewers · Ray 13d ago
cd4082bm-etched.glb cd4082bm: factory component page (tier=lcsc) · Ray 13d ago
cd4082bm-etched.step cd4082bm: factory component page (tier=lcsc) · Ray 13d ago
cd4082bm-hero.glb cd4082bm: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
cd4082bm-hero.overlay.json Publish 0.1.0 · Ray 13d ago
cd4082bm.glb Publish 0.1.0 · Ray 13d ago
cd4082bm.kicad_mod Publish 0.1.0 · Ray 13d ago
cd4082bm.kicad_sym Publish 0.1.0 · Ray 13d ago
cd4082bm.lbr Publish 0.1.0 · Ray 13d ago
cd4082bm.step Publish 0.1.0 · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago

CD4082BM

lingxingic · Logic Gates · SOP-14

CD4082BM from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Data output of gate 1; the outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.
2 1A input Data input A of gate 1; unused inputs must be connected to VDD, VSS, or another input.
3 1B input Data input B of gate 1; unused inputs must be connected to VDD, VSS, or another input.
4 1C input Data input C of gate 1; unused inputs must be connected to VDD, VSS, or another input.
5 1D input Data input D of gate 1; unused inputs must be connected to VDD, VSS, or another input.
6 n.c. unconnected Not connected.
7 VSS power_in Ground (0 V) reference for all voltages; recommended VDD is referenced to VSS.
8 n.c. unconnected Not connected.
9 2A input Data input A of gate 2; unused inputs must be connected to VDD, VSS, or another input.
10 2B input Data input B of gate 2; unused inputs must be connected to VDD, VSS, or another input.
11 2C input Data input C of gate 2; unused inputs must be connected to VDD, VSS, or another input.
12 2D input Data input D of gate 2; unused inputs must be connected to VDD, VSS, or another input.
13 2Y output Data output of gate 2; the outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.
14 VDD power_in Supply voltage; recommended range 3 V to 15 V referenced to VSS, absolute maximum +18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4082BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4082bm-etched.step / cd4082bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4082bm.step / cd4082bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (12 pp, sha256 613c5573288e00cc, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF