component

CD4081S

Public Made by Adom

by adom

GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cd4081s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4081s: viewers · Ray
cd4081s-etched.fit.json cd4081s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4081s-etched.glb cd4081s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4081s-etched.step cd4081s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4081s.glb Publish 0.1.0 · Ray
cd4081s.kicad_mod Publish 0.1.0 · Ray
cd4081s.kicad_sym Publish 0.1.0 · Ray
cd4081s.lbr Publish 0.1.0 · Ray
cd4081s.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd4081s: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd4081s: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD4081S

GR · Gates · SOP-14

CD4081S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of gate 1 (J = A AND B). CMOS logic input, high-impedance, IIN <= 1 uA @ VIN=VDD=18V.
2 B input Input B of gate 1 (J = A AND B). CMOS logic input, high-impedance.
3 J output Output J of gate 1 (J = A AND B). CMOS push-pull output; VOH >= VDD-0.05 V and VOL <= 0.05 V at
4 K output Output K of gate 2 (K = C AND D). CMOS push-pull output.
5 C input Input C of gate 2 (K = C AND D). CMOS logic input.
6 D input Input D of gate 2 (K = C AND D). CMOS logic input.
7 VSS power_in Negative supply / ground reference (0 V). Absolute maximum supply range -0.5 V to +20 V.
8 E input Input E of gate 3 (L = E AND F). CMOS logic input.
9 F input Input F of gate 3 (L = E AND F). CMOS logic input.
10 L output Output L of gate 3 (L = E AND F). CMOS push-pull output.
11 M output Output M of gate 4 (M = G AND H). CMOS push-pull output.
12 G input Input G of gate 4 (M = G AND H). CMOS logic input.
13 H input Input H of gate 4 (M = G AND H). CMOS logic input.
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V; absolute max -0.5 V to +20 V. Typical IDD = 0.01 uA @ VDD = 18V.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4081SS
  • CD4081SD

CAD (KiCad official)

  • Symbol: CD4081S
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4081s-etched.step / cd4081s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4081s.step / cd4081s.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4081s.step 195 KB You want the bare part, or you mark your own boards.
cd4081s-etched.step 2.1 MB You want the part with CD4081S already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 520 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (6 pp, sha256 72042b18c3cbd810, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF