← Commit history

cd4081s: factory component page (tier=lcsc)

Ray ·c6ce30d316 · ·parent 67dc78f
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4081s",+  "title": "CD4081S",+  "brief": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4081s"   ],+  "component": {+    "mpn": "CD4081S",+    "manufacturer": "GR",+    "package": "SOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Gates",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121628_GR-CD4081S_C22357619.pdf",+    "parts": {+      "symbol": "cd4081s.kicad_sym",+      "footprint": "cd4081s.kicad_mod",+      "model_3d": "cd4081s.glb",+      "model_3d_step": "cd4081s.step",+      "lbr": "cd4081s.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Input A of gate 1 (J = A AND B). CMOS logic input, high-impedance, IIN <= 1 uA @ VIN=VDD=18V."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Input B of gate 1 (J = A AND B). CMOS logic input, high-impedance."+      },+      {+        "number": "3",+        "name": "J",+        "type": "output",+        "description": "Output J of gate 1 (J = A AND B). CMOS push-pull output; VOH >= VDD-0.05 V and VOL <= 0.05 V at |IOUT| < 1 uA."+      },+      {+        "number": "4",+        "name": "K",+        "type": "output",+        "description": "Output K of gate 2 (K = C AND D). CMOS push-pull output."+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Input C of gate 2 (K = C AND D). CMOS logic input."+      },+      {+        "number": "6",+        "name": "D",+        "type": "input",+        "description": "Input D of gate 2 (K = C AND D). CMOS logic input."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). Absolute maximum supply range -0.5 V to +20 V."+      },+      {+        "number": "8",+        "name": "E",+        "type": "input",+        "description": "Input E of gate 3 (L = E AND F). CMOS logic input."+      },+      {+        "number": "9",+        "name": "F",+        "type": "input",+        "description": "Input F of gate 3 (L = E AND F). CMOS logic input."+      },+      {+        "number": "10",+        "name": "L",+        "type": "output",+        "description": "Output L of gate 3 (L = E AND F). CMOS push-pull output."+      },+      {+        "number": "11",+        "name": "M",+        "type": "output",+        "description": "Output M of gate 4 (M = G AND H). CMOS push-pull output."+      },+      {+        "number": "12",+        "name": "G",+        "type": "input",+        "description": "Input G of gate 4 (M = G AND H). CMOS logic input."+      },+      {+        "number": "13",+        "name": "H",+        "type": "input",+        "description": "Input H of gate 4 (M = G AND H). CMOS logic input."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Recommended operating range 3 V to 18 V; absolute max -0.5 V to +20 V. Typical IDD = 0.01 uA @ VDD = 18V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121628_GR-CD4081S_C22357619.pdf",+        "pages": 6,+        "sha256": "72042b18c3cbd810",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GR",+      "Package": "SOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4081s"+  ],+  "discovery_pitch": "CD4081S (GR) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/cd4081s-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file