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CD4081BM

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 1d ago
viewers cd4081bm: viewers · Ray 1d ago
cd4081bm-etched.glb cd4081bm: factory component page (tier=lcsc) · Ray 1d ago
cd4081bm-etched.step cd4081bm: factory component page (tier=lcsc) · Ray 1d ago
cd4081bm-hero.glb cd4081bm: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
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cd4081bm.glb Publish 0.1.0 · Ray 1d ago
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cd4081bm.lbr Publish 0.1.0 · Ray 1d ago
cd4081bm.step Publish 0.1.0 · Ray 1d ago
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README.md Initial commit: component/cd4081bm · Ray 1d ago

CD4081BM

Texas Instruments · Logic Gates · SOIC-14

CD4081BM from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Gate 1 input A; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
2 B input Gate 1 input B; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
3 J output Gate 1 AND output (A·B) with standardized symmetrical output characteristics.
4 K output Gate 2 AND output (C·D) with standardized symmetrical output characteristics.
5 C input Gate 2 input C; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
6 D input Gate 2 input D; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
7 VSS power_in Ground / negative supply terminal; all voltages are referenced to VSS.
8 E input Gate 3 input E; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
9 F input Gate 3 input F; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
10 L output Gate 3 AND output (E·F) with standardized symmetrical output characteristics.
11 M output Gate 4 AND output (G·H) with standardized symmetrical output characteristics.
12 G input Gate 4 input G; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
13 H input Gate 4 input H; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA.
14 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4081BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4081bm-etched.step / cd4081bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4081bm.step / cd4081bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 239c48fa7c2851ee, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF