component
CD4081BM
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD4081BM++**Texas Instruments** · Logic Gates · SOIC-14++CD4081BM from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gate 1 input A; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 2 | B | input | Gate 1 input B; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 3 | J | output | Gate 1 AND output (A·B) with standardized symmetrical output characteristics. |+| 4 | K | output | Gate 2 AND output (C·D) with standardized symmetrical output characteristics. |+| 5 | C | input | Gate 2 input C; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 6 | D | input | Gate 2 input D; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 7 | VSS | power_in | Ground / negative supply terminal; all voltages are referenced to VSS. |+| 8 | E | input | Gate 3 input E; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 9 | F | input | Gate 3 input F; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 10 | L | output | Gate 3 AND output (E·F) with standardized symmetrical output characteristics. |+| 11 | M | output | Gate 4 AND output (G·H) with standardized symmetrical output characteristics. |+| 12 | G | input | Gate 4 input G; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 13 | H | input | Gate 4 input H; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA. |+| 14 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4081BM`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd4081bm-etched.step` / `cd4081bm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4081bm.step` / `cd4081bm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4081b) (34 pp, sha256 `239c48fa7c2851ee`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4081bm-datasheet.pdf)
page.jsonadded+236@@ -0,0 +1,236 @@+{+ "slug": "cd4081bm",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4081bm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4081bm.kicad_sym",+ "cd4081bm.kicad_mod",+ "cd4081bm.glb",+ "cd4081bm.step",+ "cd4081bm.lbr",+ "docs/hero.png",+ "docs/cd4081bm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd4081bm-hero.glb",+ "cd4081bm-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD4081BM",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4081b",+ "parts": {+ "symbol": "cd4081bm.kicad_sym",+ "footprint": "cd4081bm.kicad_mod",+ "model_3d": "cd4081bm-hero.glb",+ "model_3d_plain": "cd4081bm.glb",+ "model_3d_step": "cd4081bm-etched.step",+ "model_3d_step_plain": "cd4081bm.step",+ "lbr": "cd4081bm.lbr"+ },+ "distributor_links": {+ "lcsc": "C353985",+ "digikey": "296-14280-5-ND",+ "mouser": "595-CD4081BM"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:25:40Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14280-5-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CD4081BM",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Gate 1 input A; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Gate 1 input B; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Gate 1 AND output (A·B) with standardized symmetrical output characteristics."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Gate 2 AND output (C·D) with standardized symmetrical output characteristics."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Gate 2 input C; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Gate 2 input D; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground / negative supply terminal; all voltages are referenced to VSS."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Gate 3 input E; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Gate 3 input F; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Gate 3 AND output (E·F) with standardized symmetrical output characteristics."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Gate 4 AND output (G·H) with standardized symmetrical output characteristics."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Gate 4 input G; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Gate 4 input H; input range -0.5 V to VDD+0.5 V, max DC input current ±10 mA."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The functional diagram is a low-quality scan, so the pin-to-signal mapping is read from a blurry ima",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 34,+ "cost_usd": 0.618,+ "at": "2026-10-08T18:25:15"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4081b",+ "pages": 34,+ "sha256": "239c48fa7c2851ee",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd4081bm.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd4081bm-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d0ab1c91b86d6e621db39bfaee6b472382ff1ed8273acaa0dd035e0668c89f26",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}