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Contents

README

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CD4081BE

Texas Instruments · Logic Gates · DIP-14

CD4081BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of the first AND gate (J = A·B).
2 B input Input B of the first AND gate (J = A·B).
3 J output Output of the first AND gate, J = A·B.
4 K output Output of the second AND gate, K = C·D.
5 C input Input C of the second AND gate (K = C·D).
6 D input Input D of the second AND gate (K = C·D).
7 VSS power_in Negative supply / ground.
8 E input Input E of the third AND gate (L = E·F).
9 F input Input F of the third AND gate (L = E·F).
10 L output Output of the third AND gate, L = E·F.
11 M output Output of the fourth AND gate, M = G·H.
12 G input Input G of the fourth AND gate (M = G·H).
13 H input Input H of the fourth AND gate (M = G·H).
14 VDD power_in Positive supply voltage.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4081BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4081be-etched.step / cd4081be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4081be.step / cd4081be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 68c6167d1ae45286, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF