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CD4081BDRG

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HANSCHIP semiconductor Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4081BDRG

HANSCHIP semiconductor · Logic Gates · SOP-14

CD4081BDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of AND gate 1; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
2 1B input Input B of AND gate 1; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
3 1Y output Buffered output of AND gate 1; the output clamp current is limited to ±10 mA in the absolute maximum ratings.
4 2Y output Buffered output of AND gate 2; the output clamp current is limited to ±10 mA in the absolute maximum ratings.
5 2A input Input A of AND gate 2; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
6 2B input Input B of AND gate 2; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
7 VSS power_in Ground reference (0 V) for the device; all voltages are referenced to VSS.
8 3A input Input A of AND gate 3; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
9 3B input Input B of AND gate 3; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
10 3Y output Buffered output of AND gate 3; the output clamp current is limited to ±10 mA in the absolute maximum ratings.
11 4Y output Buffered output of AND gate 4; the output clamp current is limited to ±10 mA in the absolute maximum ratings.
12 4A input Input A of AND gate 4; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
13 4B input Input B of AND gate 4; the datasheet limits input voltage to VSS-0.5 V to VDD+0.5 V, and unused inputs must be tied to VDD, VSS or another input.
14 VDD power_in Positive supply; recommended operating range is 3 V to 15 V referenced to VSS, with an absolute maximum of -0.5 V to +18 V.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 3
Input voltage VI -0.5 V Printed upper limit is VDD+0.5 V (not a number) 3
Output clamp current IOK -10 10 mA VO < −0.5 V or VO > VDD + 0.5 V 3
Input/output current II/O -10 10 mA 3
Operating current IDD 50 mA 3
Total power dissipation (SOP14) Ptot 500 mW SOP14 package; derate 8 mW per °C above 70 °C 3
Operating ambient temperature Tamb -40 85 ℃ 3
Storage temperature Tstg -65 150 ℃ 3
Soldering temperature TL 250 ℃ 10 s, SOP package 3
Operating supply voltage VDD 3 15 V 3
Input voltage (recommended) VI 0 V Printed upper limit is VDD (not a number) 3
Ambient temperature (recommended) Tamb -40 85 °C 3
Quiescent supply current IDD 0.25 µA VDD=5V, inputs at VDD or VSS 3
Quiescent supply current IDD 0.5 µA VDD=10V, inputs at VDD or VSS 3
Quiescent supply current IDD 1 µA VDD=15V, inputs at VDD or VSS 3
Output low-level current IOL 0.5 mA VDD=5V, VO=0.4V 3
Output low-level current IOL 1.3 mA VDD=10V, VO=0.5V 3
Output low-level current IOL 3.4 mA VDD=15V, VO=1.5V 3
Output high-level current IOH -1.4 mA VDD=5V, VO=2.5V 3
Output high-level current IOH -0.5 mA VDD=5V, VO=4.6V 3
Output high-level current IOH -1.3 mA VDD=10V, VO=9.5V 3
Output high-level current IOH -3.4 mA VDD=15V, VO=13.5V 3
Output low-level voltage VOL 0.05 V VDD=5V, /IO/<1µA 4
Output high-level voltage VOH 4.95 V VDD=5V, /IO/<1µA 4
Output high-level voltage VOH 9.95 V VDD=10V, /IO/<1µA 4
Output high-level voltage VOH 14.95 V VDD=15V, /IO/<1µA 4
Input low-level voltage VIL 1.5 V VDD=5V, /IO/<1µA 4
Input low-level voltage VIL 3 V VDD=10V, /IO/<1µA 4
Input low-level voltage VIL 4 V VDD=15V, /IO/<1µA 4
Input high-level voltage VIH 3.5 V VDD=5V, /IO/<1µA 4
Input high-level voltage VIH 7 V VDD=10V, /IO/<1µA 4
Input high-level voltage VIH 11 V VDD=15V, /IO/<1µA 4
Input capacitance CI 7.5 pF Any input port 4
Input leakage current II -0.1 0.1 µA VDD=15V 4
Propagation delay time tPHL tPHL 55 110 ns VDD=5V; tr,tf=20ns; CL=50pF 4
Propagation delay time tPHL tPHL 25 50 ns VDD=10V; tr,tf=20ns; CL=50pF 4
Propagation delay time tPHL tPHL 20 40 ns VDD=15V; tr,tf=20ns; CL=50pF 4
Propagation delay time tPLH tPLH 45 90 ns VDD=5V; tr,tf=20ns; CL=50pF 4
Propagation delay time tPLH tPLH 20 40 ns VDD=10V; tr,tf=20ns; CL=50pF 4
Propagation delay time tPLH tPLH 15 30 ns VDD=15V; tr,tf=20ns; CL=50pF 4
Transition time tTHL tTHL 60 120 ns VDD=5V; tr,tf=20ns; CL=50pF 4
Transition time tTHL tTHL 30 60 ns VDD=10V; tr,tf=20ns; CL=50pF 4
Transition time tTHL tTHL 20 40 ns VDD=15V; tr,tf=20ns; CL=50pF 4
Transition time tTLH tTLH 60 120 ns VDD=5V; tr,tf=20ns; CL=50pF 4
Transition time tTLH tTLH 30 60 ns VDD=10V; tr,tf=20ns; CL=50pF 4
Transition time tTLH tTLH 20 40 ns VDD=15V; tr,tf=20ns; CL=50pF 4

CAD (KiCad official)

  • Symbol: CD4081BDRG
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4081bdrg-etched.step / cd4081bdrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4081bdrg.step / cd4081bdrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (8 pp, sha256 13cbbca3736df91b, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF