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CD4077BPW

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Texas Instruments Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4077BPW

Texas Instruments · Logic ICs · TSSOP-14

CD4077BPW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Gate 1 input A, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
2 B input Gate 1 input B, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
3 J output Exclusive-NOR gate 1 output, high when A and B are equal per the CD4077B truth table.
4 K output Exclusive-NOR gate 2 output, high when C and D are equal per the CD4077B truth table.
5 C input Gate 2 input C, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
6 D input Gate 2 input D, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
7 VSS power_in Negative supply / ground reference for the device; absolute maximum DC supply range is -0.5 V to 20 V (VDD referenced).
8 E input Gate 3 input E, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
9 F input Gate 3 input F, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
10 L output Exclusive-NOR gate 3 output, high when E and F are equal per the CD4077B truth table.
11 M output Exclusive-NOR gate 4 output, high when G and H are equal per the CD4077B truth table.
12 G input Gate 4 input G, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
13 H input Gate 4 input H, protected by the CMOS protection network; DC input current is limited to ±10 mA and input voltage must stay within -0.5 V to VDD + 0.5 V.
14 VDD power_in Positive supply; the datasheet gives a typical supply range of 3 V to 18 V and an absolute maximum of 20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (typical) VDD 3 18 V 4
Temperature range TA -55 125 °C 4
DC supply voltage range VDD -0.5 20 V 4
Input voltage range, all inputs -0.5 V 4
DC input current -10 10 mA 4
Maximum junction temperature (plastic package) TJ 150 °C 4
Maximum storage temperature range Tstg -65 150 °C 4
Quiescent device current IDD 0.01 0.25 µA TA 25°C; VIN 0, 5 V; VDD 5 V 4
Quiescent device current IDD 0.01 0.5 µA TA 25°C; VIN 0, 10 V; VDD 10 V 4
Quiescent device current IDD 0.01 1 µA TA 25°C; VIN 0, 15 V; VDD 15 V 4
Quiescent device current IDD 0.02 5 µA TA 25°C; VIN 0, 20 V; VDD 20 V 4
Output low (sink) current IOL 0.51 1 mA TA 25°C; VO 0.4 V; VIN 0, 5 V; VDD 5 V 4
Output low (sink) current IOL 1.3 2.6 mA TA 25°C; VO 0.5 V; VIN 0, 10 V; VDD 10 V 4
Output low (sink) current IOL 3.4 6.8 mA TA 25°C; VO 1.5 V; VIN 0, 15 V; VDD 15 V 4
Output high (source) current IOH -0.51 -1 mA TA 25°C; VO 4.6 V; VIN 0, 5 V; VDD 5 V 4
Output high (source) current IOH -1.6 -3.2 mA TA 25°C; VO 2.5 V; VIN 0, 5 V; VDD 5 V 4
Output high (source) current IOH -1.3 -2.6 mA TA 25°C; VO 9.5 V; VIN 0, 10 V; VDD 10 V 4
Output high (source) current IOH -3.4 -6.8 mA TA 25°C; VO 13.5 V; VIN 0, 15 V; VDD 15 V 4
Output voltage low level VOL 0 0.05 V TA 25°C; VIN 0, 5 V; VDD 5 V 4
Output voltage high level VOH 4.95 5 V TA 25°C; VIN 0, 5 V; VDD 5 V 4
Output voltage high level VOH 9.95 10 V TA 25°C; VIN 0, 10 V; VDD 10 V 4
Output voltage high level VOH 14.95 15 V TA 25°C; VIN 0, 15 V; VDD 15 V 4
Input low voltage VIL 1.5 V TA 25°C; VO 0.5, 4.5 V; VDD 5 V 4
Input low voltage VIL 3 V TA 25°C; VO 1, 9 V; VDD 10 V 4
Input low voltage VIL 4 V TA 25°C; VO 1.5, 13.5 V; VDD 15 V 4
Input high voltage VIH 3.5 V TA 25°C; VO 0.5, 4.5 V; VDD 5 V 4
Input high voltage VIH 7 V TA 25°C; VO 1, 9 V; VDD 10 V 4
Input high voltage VIH 11 V TA 25°C; VO 1.5, 13.5 V; VDD 15 V 4
Input current IIN -0.1 0.1 µA TA 25°C; VIN 0, 18 V; VDD 18 V 4
Quiescent device current IDD 7.5 µA TA 125°C; VIN 0, 5 V; VDD 5 V 4
Quiescent device current IDD 15 µA TA 125°C; VIN 0, 10 V; VDD 10 V 4
Quiescent device current IDD 30 µA TA 125°C; VIN 0, 15 V; VDD 15 V 4
Quiescent device current IDD 150 µA TA 125°C; VIN 0, 20 V; VDD 20 V 4
Output low (sink) current IOL 0.36 mA TA 125°C; VO 0.4 V; VIN 0, 5 V; VDD 5 V 4
Output low (sink) current IOL 0.9 mA TA 125°C; VO 0.5 V; VIN 0, 10 V; VDD 10 V 4
Output low (sink) current IOL 2.4 mA TA 125°C; VO 1.5 V; VIN 0, 15 V; VDD 15 V 4
Output high (source) current IOH -0.36 mA TA 125°C; VO 4.6 V; VIN 0, 5 V; VDD 5 V 4
Output high (source) current IOH -1.15 mA TA 125°C; VO 2.5 V; VIN 0, 5 V; VDD 5 V 4
Output high (source) current IOH -0.9 mA TA 125°C; VO 9.5 V; VIN 0, 10 V; VDD 10 V 4
Output high (source) current IOH -2.4 mA TA 125°C; VO 13.5 V; VIN 0, 15 V; VDD 15 V 4
Input current IIN -1 1 µA TA 125°C; VIN 0, 18 V; VDD 18 V 4
Propagation delay time tPHL, tPLH 140 280 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 5 V 5
Propagation delay time tPHL, tPLH 65 130 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 10 V 5
Propagation delay time tPHL, tPLH 50 100 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 15 V 5
Transition time tTHL, tTLH 100 200 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 5 V 5
Transition time tTHL, tTLH 50 100 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 10 V 5
Transition time tTHL, tTLH 40 80 ns TA 25°C; tr, tf 20 ns; CL 50 pF; RL 200 kΩ; VDD 15 V 5
Package thermal impedance, PW (TSSOP) package θJA 113 °C/W JESD 51-7 (see Note 1) 4
Input capacitance CIN 7.5 pF Any input; VDD 5 V; TA 25°C 5

CAD (KiCad official)

  • Symbol: CD4077BPW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4077bpw-etched.step / cd4077bpw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4077bpw.step / cd4077bpw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 2c6477df1a6cc4c1, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF