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docs cd4077bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cd4077bm96: viewers · Ray 1mo ago
cd4077bm96-etched.fit.json cd4077bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4077bm96-etched.glb cd4077bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
cd4077bm96-etched.step cd4077bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
cd4077bm96.glb Publish 0.1.0 · Ray 1mo ago
cd4077bm96.kicad_mod Publish 0.1.0 · Ray 1mo ago
cd4077bm96.kicad_sym Publish 0.1.0 · Ray 1mo ago
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cd4077bm96.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json cd4077bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
README.md cd4077bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4077BM96

Texas Instruments · Gates · SOIC-14

CD4077BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of gate 1 (XNOR gate J). CMOS logic input, VIH >= 3.5 V at VDD=5 V, 7 V at VDD=10 V, 11 V at VDD=15 V; input current +/-0.1 uA max at VDD=18 V.
2 B input Input B of gate 1 (XNOR gate J). CMOS logic input paired with pin 1; J = A XNOR B.
3 J output Output of gate 1: J = A XNOR B (NOT(A XOR B)). CMOS push-pull output; sources/sinks per DC electrical specs (e.g. IOH/IOL >= 0.51 mA at VDD=5 V, 1.3 mA at 10 V, 3.4 mA at 15 V).
4 K output Output of gate 2: K = C XNOR D. CMOS push-pull output; standardized symmetrical drive characteristics.
5 C input Input C of gate 2 (XNOR gate K). CMOS logic input.
6 D input Input D of gate 2 (XNOR gate K). CMOS logic input paired with pin 5.
7 VSS power_in Negative supply / ground reference. Typically 0 V. VDD-VSS range 3 V to 18 V operating (20 V absolute max).
8 E input Input E of gate 3 (XNOR gate L). CMOS logic input.
9 F input Input F of gate 3 (XNOR gate L). CMOS logic input paired with pin 8.
10 L output Output of gate 3: L = E XNOR F. CMOS push-pull output.
11 M output Output of gate 4: M = G XNOR H. CMOS push-pull output.
12 G input Input G of gate 4 (XNOR gate M). CMOS logic input.
13 H input Input H of gate 4 (XNOR gate M). CMOS logic input paired with pin 12.
14 VDD power_in Positive supply voltage. Operating range 3 V to 18 V (20 V absolute max). Quiescent current IDD 0.25 uA typ at VDD=5 V, 5 uA typ at VDD=20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4077BM96
  • CD4077BM96BMT
  • CD4077BM96BME4
  • CD4077BM96BMG4
  • CD4077BM96E4
  • CD4077BM96G4
  • CD4077BM96BMTE4
  • CD4077BM96BMTG4
  • CD4077BM96BE
  • CD4077BM96BEE4
  • CD4077BM96BF
  • CD4077BM96BF3A
  • CD4077BM96BNSR
  • CD4077BM96BNSRE4
  • CD4077BM96BNSRG4
  • CD4077BM96BPW
  • CD4077BM96BPWR
  • CD4077BM96BPWE4
  • CD4077BM96BPWG4
  • CD4077BM96BPWRE4
  • CD4077BM96BPWRG4

CAD (KiCad official)

  • Symbol: CD4077BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4077bm96-etched.step / cd4077bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4077bm96.step / cd4077bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 ef734006676742da, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF