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CD4077BE

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HGSEMI Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4077BE

HGSEMI · Logic Gates · DIP-14

CD4077BE from HGSEMI, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of gate 1; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
2 1B input Data input of gate 1; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
3 1Y output Data output of gate 1; the outputs are fully buffered, giving the highest noise immunity and pattern insensitivity to output impedance.
4 2Y output Data output of gate 2; the outputs are fully buffered, giving the highest noise immunity and pattern insensitivity to output impedance.
5 2A input Data input of gate 2; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
6 2B input Data input of gate 2; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
7 VSS power_in Ground (0 V) reference for all voltages on the device.
8 3A input Data input of gate 3; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
9 3B input Data input of gate 3; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
10 3Y output Data output of gate 3; the outputs are fully buffered, giving the highest noise immunity and pattern insensitivity to output impedance.
11 4Y output Data output of gate 4; the outputs are fully buffered, giving the highest noise immunity and pattern insensitivity to output impedance.
12 4A input Data input of gate 4; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
13 4B input Data input of gate 4; all inputs are rated -0.5 V to VDD+0.5 V with DC input current limited to ±10 mA, and unused inputs must be tied to VDD, VSS, or another input.
14 VDD power_in Supply voltage; recommended range is 3 V to 15 V referenced to VSS, with an absolute maximum of +18 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 4
DC input current IIK -10 10 mA any one input 4
input voltage VI -0.5 V all inputs; printed max is VDD+0.5 4
storage temperature Tstg -65 150 ℃ 4
soldering temperature TL 245 ℃ 10s 4
total power dissipation Ptot 500 mW 4
device dissipation per output transistor P 100 mW per output transistor 4
supply voltage VDD 3 15 V 4
ambient temperature Tamb -40 85 ℃ in free air 4
supply current IDD 0.01 0.25 μA Tamb=25℃; VIN=0,5 V; VDD=5 V 5
supply current IDD 0.01 0.5 μA Tamb=25℃; VIN=0,10 V; VDD=10 V 5
supply current IDD 0.01 1 μA Tamb=25℃; VIN=0,15 V; VDD=15 V 5
LOW-level output current IOL 0.51 1 mA Tamb=25℃; VO=0.4 V; VIN=0,5 V; VDD=5 V 5
LOW-level output current IOL 1.3 2.6 mA Tamb=25℃; VO=0.5 V; VIN=0,10 V; VDD=10 V 5
LOW-level output current IOL 3.4 6.8 mA Tamb=25℃; VO=1.5 V; VIN=0,15 V; VDD=15 V 5
HIGH-level output current IOH -0.51 -1 mA Tamb=25℃; VO=4.6 V; VIN=0,5 V; VDD=5 V 5
HIGH-level output current IOH -1.6 -3.2 mA Tamb=25℃; VO=2.5 V; VIN=0,5 V; VDD=5 V 5
HIGH-level output current IOH -1.3 -2.6 mA Tamb=25℃; VO=9.5 V; VIN=0,10 V; VDD=10 V 5
HIGH-level output current IOH -3.4 -6.8 mA Tamb=25℃; VO=13.5 V; VIN=0,15 V; VDD=15 V 5
LOW-level output voltage VOL 0 0.05 V Tamb=25℃; VIN=0,5 V; VDD=5 V 5
HIGH-level output voltage VOH 4.95 5 V Tamb=25℃; VIN=0,5 V; VDD=5 V 5
HIGH-level output voltage VOH 9.95 10 V Tamb=25℃; VIN=0,10 V; VDD=10 V 5
HIGH-level output voltage VOH 14.95 15 V Tamb=25℃; VIN=0,15 V; VDD=15 V 5
LOW-level input voltage VIL 1.5 V Tamb=25℃; VO=0.5,4.5 V; VDD=5 V 5
LOW-level input voltage VIL 3 V Tamb=25℃; VO=1,9 V; VDD=10 V 5
LOW-level input voltage VIL 4 V Tamb=25℃; VO=1.5,13.5 V; VDD=15 V 5
HIGH-level input voltage VIH 3.5 V Tamb=25℃; VO=0.5,4.5 V; VDD=5 V 5
HIGH-level input voltage VIH 7 V Tamb=25℃; VO=1,9 V; VDD=10 V 5
HIGH-level input voltage VIH 11 V Tamb=25℃; VO=1.5,13.5 V; VDD=15 V 5
propagation delay time tPHL, tPLH 140 280 ns see Figure 4; VDD=5V; CL=50pF; Tamb=25℃ 6
propagation delay time tPHL, tPLH 65 130 ns see Figure 4; VDD=10V; CL=50pF; Tamb=25℃ 6
propagation delay time tPHL, tPLH 50 100 ns see Figure 4; VDD=15V; CL=50pF; Tamb=25℃ 6
transition time tTHL, tTLH 100 200 ns see Figure 4; VDD=5V; CL=50pF; Tamb=25℃ 6
transition time tTHL, tTLH 50 100 ns see Figure 4; VDD=10V; CL=50pF; Tamb=25℃ 6
transition time tTHL, tTLH 40 80 ns see Figure 4; VDD=15V; CL=50pF; Tamb=25℃ 6
input capacitance CI 5 7.5 pF any input 6
supply current IDD 7.5 μA Tamb=+85℃; VIN=0,5 V; VDD=5 V 6
supply current IDD 15 μA Tamb=+85℃; VIN=0,10 V; VDD=10 V 6
supply current IDD 30 μA Tamb=+85℃; VIN=0,15 V; VDD=15 V 6
LOW-level output current IOL 0.42 mA Tamb=+85℃; VO=0.4 V; VIN=0,5 V; VDD=5 V 6
LOW-level output current IOL 1.1 mA Tamb=+85℃; VO=0.5 V; VIN=0,10 V; VDD=10 V 6
LOW-level output current IOL 2.8 mA Tamb=+85℃; VO=1.5 V; VIN=0,15 V; VDD=15 V 6
HIGH-level output current IOH -0.42 mA Tamb=+85℃; VO=4.6 V; VIN=0,5 V; VDD=5 V 6
HIGH-level output current IOH -1.3 mA Tamb=+85℃; VO=2.5 V; VIN=0,5 V; VDD=5 V 6
HIGH-level output current IOH -1.1 mA Tamb=+85℃; VO=9.5 V; VIN=0,10 V; VDD=10 V 6
HIGH-level output current IOH -2.8 mA Tamb=+85℃; VO=13.5 V; VIN=0,15 V; VDD=15 V 6
LOW-level output voltage VOL 0.05 V Tamb=+85℃; VIN=0,5 V; VDD=5 V 6
HIGH-level output voltage VOH 4.95 V Tamb=+85℃; VIN=0,5 V; VDD=5 V 6
HIGH-level output voltage VOH 9.95 V Tamb=+85℃; VIN=0,10 V; VDD=10 V 6
HIGH-level output voltage VOH 14.95 V Tamb=+85℃; VIN=0,15 V; VDD=15 V 6
LOW-level input voltage VIL 1.5 V Tamb=+85℃; VO=0.5,4.5 V; VDD=5 V 6
LOW-level input voltage VIL 3 V Tamb=+85℃; VO=1,9 V; VDD=10 V 6
LOW-level input voltage VIL 4 V Tamb=+85℃; VO=1.5,13.5 V; VDD=15 V 6
HIGH-level input voltage VIH 3.5 V Tamb=+85℃; VO=0.5,4.5 V; VDD=5 V 6
HIGH-level input voltage VIH 7 V Tamb=+85℃; VO=1,9 V; VDD=10 V 6
HIGH-level input voltage VIH 11 V Tamb=+85℃; VO=1.5,13.5 V; VDD=15 V 6

CAD (KiCad official)

  • Symbol: CD4077BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4077be-etched.step / cd4077be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4077be.step / cd4077be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (11 pp, sha256 e89f7732a9f387e4, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF