main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers cd4075bpwr: viewers · Ray 8d ago
cd4075bpwr-etched.glb Publish 0.1.0 · Ray 8d ago
cd4075bpwr-etched.step cd4075bpwr: factory component page (tier=mfr) · Ray 8d ago
cd4075bpwr-hero.glb cd4075bpwr: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
cd4075bpwr-hero.overlay.json Publish 0.1.0 · Ray 8d ago
cd4075bpwr.glb Publish 0.1.0 · Ray 8d ago
cd4075bpwr.kicad_mod Publish 0.1.0 · Ray 8d ago
cd4075bpwr.kicad_sym Publish 0.1.0 · Ray 8d ago
cd4075bpwr.lbr Publish 0.1.0 · Ray 8d ago
cd4075bpwr.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

CD4075BPWR

Texas Instruments · Logic Gates · TSSOP-14

CD4075BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Gate 1 input A, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
2 B1 input Gate 1 input B, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
3 A2 input Gate 2 input A, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
4 B2 input Gate 2 input B, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
5 C2 input Gate 2 input C, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
6 J2 output Gate 2 output, the 3-input OR of pins 3, 4 and 5.
7 VSS power_in Ground reference (VSS); all supply voltages are referenced to this terminal.
8 C1 input Gate 1 input C, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
9 J1 output Gate 1 output, the 3-input OR of pins 1, 2 and 8.
10 J3 output Gate 3 output, the 3-input OR of pins 11, 12 and 13.
11 A3 input Gate 3 input A, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
12 B3 input Gate 3 input B, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
13 C3 input Gate 3 input C, protected by CMOS input network, limited to -0.5V to VDD+0.5V.
14 VDD power_in Positive supply; absolute maximum -0.5V to +20V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4075BPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4075bpwr-etched.step / cd4075bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4075bpwr.step / cd4075bpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 e6108f3d67797b70, retrieved 2026-10-20, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF