component

CD4075BM96

Public Made by Adom

by adom

Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4075bm96factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers cd4075bm96: viewers · Ray 5d ago
cd4075bm96-etched.glb Publish 0.1.0 · Ray 5d ago
cd4075bm96-etched.step cd4075bm96: factory component page (tier=mfr) · Ray 5d ago
cd4075bm96-hero.glb cd4075bm96: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
cd4075bm96-hero.overlay.json Publish 0.1.0 · Ray 5d ago
cd4075bm96.glb Publish 0.1.0 · Ray 5d ago
cd4075bm96.kicad_mod Publish 0.1.0 · Ray 5d ago
cd4075bm96.kicad_sym Publish 0.1.0 · Ray 5d ago
cd4075bm96.lbr Publish 0.1.0 · Ray 5d ago
cd4075bm96.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

CD4075BM96

Texas Instruments · Logic Gates · SOIC-14

CD4075BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C input Gate J input C; inputs are limited to -0.5V to VDD+0.5V.
2 B input Gate J input B; inputs are limited to -0.5V to VDD+0.5V.
3 F input Gate K input F; inputs are limited to -0.5V to VDD+0.5V.
4 E input Gate K input E; inputs are limited to -0.5V to VDD+0.5V.
5 D input Gate K input D; inputs are limited to -0.5V to VDD+0.5V.
6 K output Output of gate K, the OR of inputs D, E and F.
7 VSS power_in Ground / negative supply terminal, the reference for VDD.
8 A input Gate J input A; inputs are limited to -0.5V to VDD+0.5V.
9 J output Output of gate J, the OR of inputs A, B and C.
10 L output Output of gate L, the OR of inputs G, H and I.
11 I input Gate L input I; inputs are limited to -0.5V to VDD+0.5V.
12 H input Gate L input H; inputs are limited to -0.5V to VDD+0.5V.
13 G input Gate L input G; inputs are limited to -0.5V to VDD+0.5V.
14 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5V to +20V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature range (orderable device, Op Temp column) -55 125 °C 17

CAD (KiCad official)

  • Symbol: CD4075BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4075bm96-etched.step / cd4075bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4075bm96.step / cd4075bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 b252d5f777c3c2b5, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF