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CD4075BM

Public Made by Adom

by adom

lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4075BM

lingxingic · Logic Gates · SOP-14

CD4075BM from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2A input Data input 2A of the second OR gate; unused inputs must be connected to VDD, GND, or another input.
2 2B input Data input 2B of the second OR gate; unused inputs must be connected to VDD, GND, or another input.
3 1A input Data input 1A of the first OR gate; unused inputs must be connected to VDD, GND, or another input.
4 1B input Data input 1B of the first OR gate; unused inputs must be connected to VDD, GND, or another input.
5 1C input Data input 1C of the first OR gate; unused inputs must be connected to VDD, GND, or another input.
6 1Y output Data output of the first OR gate; the output is fully buffered.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 2C input Data input 2C of the second OR gate; unused inputs must be connected to VDD, GND, or another input.
9 2Y output Data output of the second OR gate; the output is fully buffered.
10 3Y output Data output of the third OR gate; the output is fully buffered.
11 3C input Data input 3C of the third OR gate; unused inputs must be connected to VDD, GND, or another input.
12 3B input Data input 3B of the third OR gate; unused inputs must be connected to VDD, GND, or another input.
13 3A input Data input 3A of the third OR gate; unused inputs must be connected to VDD, GND, or another input.
14 VDD power_in Supply voltage, recommended range 3 V to 15 V referenced to GND; absolute maximum 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 6
DC input current IIK -10 10 mA any one input 6
input voltage VI -0.5 V all inputs 6
storage temperature Tstg -65 150 ℃ 6
total power dissipation Ptot 500 mW 6
device dissipation P 100 mW per output transistor 6
soldering temperature TL 260 ℃ 10s, SOP/TSSOP 6
supply voltage VDD 3 15 V 7
ambient temperature Tamb -40 125 ℃ in free air 7
supply current IDD 1 uA VO -; VIN 0, 5 V; VDD 5 V 7
input leakage current II -1 1 uA VO -; VIN 0, 15 V; VDD 15 V 7
LOW-level output current IOL 0.51 1 mA VO 0.4 V; VIN 0, 5 V; VDD 5 V 7
LOW-level output current IOL 1.3 2.6 mA VO 0.5 V; VIN 0, 10 V; VDD 10 V 7
LOW-level output current IOL 3.4 6.8 mA VO 1.5 V; VIN 0, 15 V; VDD 15 V 7
HIGH-level output current IOH -0.51 -1 mA VO 4.6 V; VIN 0, 5 V; VDD 5 V 7
HIGH-level output current IOH -1.6 -3.2 mA VO 2.5 V; VIN 0, 5 V; VDD 5 V 7
HIGH-level output current IOH -1.3 -2.6 mA VO 9.5 V; VIN 0, 10 V; VDD 10 V 7
HIGH-level output current IOH -3.4 -6.8 mA VO 13.5 V; VIN 0, 15 V; VDD 15 V 7
LOW-level output voltage VOL 0 0.05 V VIN 0, 5 V; VDD 5 V 7
HIGH-level output voltage VOH 4.95 5 V VIN 0, 5 V; VDD 5 V 7
HIGH-level output voltage VOH 9.95 10 V VIN 0, 10 V; VDD 10 V 7
HIGH-level output voltage VOH 14.95 15 V VIN 0, 15 V; VDD 15 V 7
LOW-level input voltage VIL 1.5 V VO 0.5, 4.5 V; VDD 5 V 7
LOW-level input voltage VIL 3 V VO 1, 9 V; VDD 10 V 7
LOW-level input voltage VIL 4 V VO 1.5, 13.5 V; VDD 15 V 7
HIGH-level input voltage VIH 3.5 V VO 4.5 V; VDD 5 V 7
HIGH-level input voltage VIH 7 V VO 9 V; VDD 10 V 7
HIGH-level input voltage VIH 11 V VO 13.5 V; VDD 15 V 7
propagation delay time tPHL, tPLH 125 250 ns see Figure 4; VDD=5V 8
propagation delay time tPHL, tPLH 60 120 ns see Figure 4; VDD=10V 8
propagation delay time tPHL, tPLH 45 90 ns see Figure 4; VDD=15V 8
transition time tTHL, tTLH 100 200 ns see Figure 4; VDD=5V 8
transition time tTHL, tTLH 50 100 ns see Figure 4; VDD=10V 8
transition time tTHL, tTLH 40 80 ns see Figure 4; VDD=15V 8
input capacitance CI 5 7.5 pF any input 8

CAD (KiCad official)

  • Symbol: CD4075BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4075bm-etched.step / cd4075bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4075bm.step / cd4075bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (13 pp, sha256 04212aa671a012ba, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF