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Contents

README

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CD4073BPWR

Texas Instruments · Logic Gates · TSSOP-14

CD4073BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of AND gate 1 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
2 1B input Input B of AND gate 1 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
3 2B input Input B of AND gate 2 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
4 2A input Input A of AND gate 2 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
5 2C input Input C of AND gate 2 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
6 2Y output Output of AND gate 2 (Y = A•B•C), CMOS push-pull output providing the sink/source drive currents (IOL/IOH) listed in the static electrical characteristics table.
7 VSS power_in Negative supply / ground reference pin; all device voltages, including VDD (-0.5V to +20V) and input levels, are referenced to this terminal.
8 1C input Input C of AND gate 1 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
9 1Y output Output of AND gate 1 (Y = A•B•C), CMOS push-pull output providing the sink/source drive currents (IOL/IOH) listed in the static electrical characteristics table.
10 3Y output Output of AND gate 3 (Y = A•B•C), CMOS push-pull output providing the sink/source drive currents (IOL/IOH) listed in the static electrical characteristics table.
11 3C input Input C of AND gate 3 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
12 3A input Input A of AND gate 3 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
13 3B input Input B of AND gate 3 (one of three inputs of a 3-input AND gate); input voltage range -0.5V to VDD+0.5V, DC input current limit ±10mA.
14 VDD power_in Positive supply pin; DC supply-voltage range -0.5V to +20V referenced to VSS, recommended operating supply-voltage range 3V to 18V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4073BPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4073bpwr-etched.step / cd4073bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4073bpwr.step / cd4073bpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 68c6167d1ae45286, retrieved 2026-09-29, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF