CD4073BM

{
  "slug": "cd4073bm",
  "version": "0.1.0",
  "type": "component",
  "description": "HGSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4073bm",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4073bm.kicad_sym",
    "cd4073bm.kicad_mod",
    "cd4073bm.glb",
    "cd4073bm.step",
    "cd4073bm.lbr",
    "docs/hero.png",
    "docs/cd4073bm-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4073bm-hero.glb",
    "cd4073bm-hero.overlay.json",
    "cd4073bm-etched.glb"
  ],
  "component": {
    "mpn": "CD4073BM",
    "manufacturer": "HGSEMI",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8770706818295717888",
    "parts": {
      "symbol": "cd4073bm.kicad_sym",
      "footprint": "cd4073bm.kicad_mod",
      "model_3d": "cd4073bm-hero.glb",
      "model_3d_plain": "cd4073bm-etched.glb",
      "model_3d_step": "cd4073bm-etched.step",
      "model_3d_step_plain": "cd4073bm.step",
      "lbr": "cd4073bm.lbr"
    },
    "distributor_links": {
      "lcsc": "C5310766"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T22:36:11Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Gate input A of the CD4073B triple AND gate; CMOS input protected, input voltage limited to -0.5 V to +0.5 V per the ratings table."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Gate input B of the CD4073B triple AND gate; CMOS input protected, maximum input current 1 µA at 18 V over temperature."
      },
      {
        "number": "3",
        "name": "D",
        "type": "input",
        "description": "Gate input D of the CD4073B triple AND gate; CMOS input protected, maximum DC input current 10 mA."
      },
      {
        "number": "4",
        "name": "E",
        "type": "input",
        "description": "Gate input E of the CD4073B triple AND gate; CMOS input protected, input capacitance 5 pF typ."
      },
      {
        "number": "5",
        "name": "F",
        "type": "input",
        "description": "Gate input F of the CD4073B triple AND gate; CMOS input protected, input capacitance 7.5 pF max."
      },
      {
        "number": "6",
        "name": "K",
        "type": "output",
        "description": "Gate output K of the CD4073B, with standardized symmetrical output characteristics (VOL max 0.05 V, VOH min 4.95 V at VDD=5 V)."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground / negative supply terminal; all voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "C",
        "type": "input",
        "description": "Gate input C of the CD4073B triple AND gate; CMOS input protected, VIL max 1.5 V and VIH min 3.5 V at VDD=5 V."
      },
      {
        "number": "9",
        "name": "J",
        "type": "output",
        "description": "Gate output J of the CD4073B, with propagation delay typ. 60 ns at VDD=10 V."
      },
      {
        "number": "10",
        "name": "L",
        "type": "output",
        "description": "Gate output L of the CD4073B, with standardized symmetrical output characteristics and transition time typ. 50 ns at VDD=10 V."
      },
      {
        "number": "11",
        "name": "I",
        "type": "input",
        "description": "Gate input I of the CD4073B triple AND gate; CMOS input protected, noise margin 1 V at VDD=5 V."
      },
      {
        "number": "12",
        "name": "H",
        "type": "input",
        "description": "Gate input H of the CD4073B triple AND gate; CMOS input protected, noise margin 2 V at VDD=10 V."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Gate input G of the CD4073B triple AND gate; CMOS input protected, noise margin 2.5 V at VDD=15 V."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; recommended 5 V to 15 V, absolute maximum -0.5 V to +20 V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-configuration drawing on page 4 labels the pins by letter only (A–L). The text and the drawi; The datasheet covers DIP, SOP and TSSOP with one shared drawing. CD4073BM/TR is listed as SOP-14, so",
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 11,
        "cost_usd": 0.3557,
        "at": "2026-10-17T22:34:07"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8770706818295717888",
        "pages": 11,
        "sha256": "05467aba098f95c2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4073bm.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4073bm-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6dfd1fadc0a45e82d9c4a4da5a297f31c40c10b07a4d87372e3b1fab44599081",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}