# CD4072NS14ARDQ

**GR** · Logic Gates · SOP-14

CD4072NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output of OR gate 1, the logic OR of inputs 1A to 1D. |
| 2 | 1A | input | Data input A of OR gate 1; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 3 | 1B | input | Data input B of OR gate 1; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 4 | 1C | input | Data input C of OR gate 1; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 5 | 1D | input | Data input D of OR gate 1; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 6 | NC | unconnected | Not connected; the datasheet states no function for this pin. |
| 7 | VSS | power_in | Ground reference (0 V) for all voltages and the negative supply terminal of the device. |
| 8 | NC | unconnected | Not connected; the datasheet states no function for this pin. |
| 9 | 2A | input | Data input A of OR gate 2; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 10 | 2B | input | Data input B of OR gate 2; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 11 | 2C | input | Data input C of OR gate 2; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 12 | 2D | input | Data input D of OR gate 2; input voltage must stay within -0.5 V to VDD+0.5 V (absolute maximum ratings). |
| 13 | 2Y | output | Data output of OR gate 2, the logic OR of inputs 2A to 2D. |
| 14 | VDD | power_in | Positive supply voltage; absolute maximum DC supply is -0.5 V to 20 V referenced to VSS, with parametric ratings at 5 V, 10 V and 15 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `CD4072NS14ARDQ`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4072ns14ardq-etched.step` / `cd4072ns14ardq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4072ns14ardq.step` / `cd4072ns14ardq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388398241931264) (7 pp, sha256 `56a3a325e64db14f`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4072ns14ardq-datasheet.pdf)