CD4072BPW

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4072bpw",
  "title": "CD4072BPW",
  "brief": "Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4072bpw",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "CD4072BPW",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4072b.pdf",
    "parts": {
      "symbol": "cd4072bpw.kicad_sym",
      "footprint": "cd4072bpw.kicad_mod",
      "model_3d": "cd4072bpw-hero.glb",
      "model_3d_plain": "cd4072bpw.glb",
      "model_3d_step": "cd4072bpw-etched.step",
      "model_3d_step_plain": "cd4072bpw.step",
      "lbr": "cd4072bpw.lbr"
    },
    "distributor_links": {
      "lcsc": "C2877139",
      "digikey": "296-32907-5-ND",
      "mouser": "595-CD4072BPW"
    },
    "distributor_check": {
      "checked_at": "2026-10-07T20:57:20Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-32907-5-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-CD4072BPW",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "J",
        "type": "output",
        "description": "Output of OR gate 1 (J = A+B+C+D); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C."
      },
      {
        "number": "2",
        "name": "A",
        "type": "input",
        "description": "Gate 1 input A; input voltage range -0.5 V to VDD+0.5 V, max input current 1 µA at 18 V over full temperature range."
      },
      {
        "number": "3",
        "name": "B",
        "type": "input",
        "description": "Gate 1 input B; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "4",
        "name": "C",
        "type": "input",
        "description": "Gate 1 input C; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "5",
        "name": "D",
        "type": "input",
        "description": "Gate 1 input D; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "6",
        "name": "NC",
        "type": "unconnected",
        "description": "Not shown in the CD4072B functional diagram; no internal connection indicated."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground / negative supply reference; all VDD voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "NC",
        "type": "unconnected",
        "description": "Not shown in the CD4072B functional diagram; no internal connection indicated."
      },
      {
        "number": "9",
        "name": "E",
        "type": "input",
        "description": "Gate 2 input E; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "10",
        "name": "F",
        "type": "input",
        "description": "Gate 2 input F; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "11",
        "name": "G",
        "type": "input",
        "description": "Gate 2 input G; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "12",
        "name": "H",
        "type": "input",
        "description": "Gate 2 input H; input voltage range -0.5 V to VDD+0.5 V."
      },
      {
        "number": "13",
        "name": "K",
        "type": "output",
        "description": "Output of OR gate 2 (K = E+F+G+H); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The functional diagram on page 1 is low resolution; the J output pin number (1) is not legible and w; Pins 6 and 8 do not appear in the CD4072B functional diagram, so they were marked as no-connect. The",
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 34,
        "cost_usd": 0.5971,
        "at": "2026-10-07T20:57:02"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4072b.pdf",
        "pages": 34,
        "sha256": "e6108f3d67797b70",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4072bpw.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5,
          1
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4072bpw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5,
          1
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "409e9ac77428cfd9de44b024aa7786f6d395f0e0a3e34e0c29816b33cbdafdc1",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "TSSOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4072bpw"
  ],
  "discovery_pitch": "CD4072BPW (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4072bpw.kicad_sym",
    "cd4072bpw.kicad_mod",
    "cd4072bpw.glb",
    "cd4072bpw.step",
    "cd4072bpw.lbr",
    "docs/hero.png",
    "docs/cd4072bpw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4072bpw-hero.glb",
    "cd4072bpw-hero.overlay.json"
  ],
  "visibility": {
    "public": true
  }
}