component
CD4072BPW
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4072BPW
Texas Instruments · Logic Gates · TSSOP-14
CD4072BPW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | J | output | Output of OR gate 1 (J = A+B+C+D); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C. |
| 2 | A | input | Gate 1 input A; input voltage range -0.5 V to VDD+0.5 V, max input current 1 µA at 18 V over full temperature range. |
| 3 | B | input | Gate 1 input B; input voltage range -0.5 V to VDD+0.5 V. |
| 4 | C | input | Gate 1 input C; input voltage range -0.5 V to VDD+0.5 V. |
| 5 | D | input | Gate 1 input D; input voltage range -0.5 V to VDD+0.5 V. |
| 6 | NC | unconnected | Not shown in the CD4072B functional diagram; no internal connection indicated. |
| 7 | VSS | power_in | Ground / negative supply reference; all VDD voltages are referenced to VSS. |
| 8 | NC | unconnected | Not shown in the CD4072B functional diagram; no internal connection indicated. |
| 9 | E | input | Gate 2 input E; input voltage range -0.5 V to VDD+0.5 V. |
| 10 | F | input | Gate 2 input F; input voltage range -0.5 V to VDD+0.5 V. |
| 11 | G | input | Gate 2 input G; input voltage range -0.5 V to VDD+0.5 V. |
| 12 | H | input | Gate 2 input H; input voltage range -0.5 V to VDD+0.5 V. |
| 13 | K | output | Output of OR gate 2 (K = E+F+G+H); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C. |
| 14 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4072BPW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4072bpw-etched.step/cd4072bpw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4072bpw.step/cd4072bpw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
e6108f3d67797b70, retrieved 2026-10-07, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4072BPW
**Texas Instruments** · Logic Gates · TSSOP-14
CD4072BPW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | J | output | Output of OR gate 1 (J = A+B+C+D); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C. |
| 2 | A | input | Gate 1 input A; input voltage range -0.5 V to VDD+0.5 V, max input current 1 µA at 18 V over full temperature range. |
| 3 | B | input | Gate 1 input B; input voltage range -0.5 V to VDD+0.5 V. |
| 4 | C | input | Gate 1 input C; input voltage range -0.5 V to VDD+0.5 V. |
| 5 | D | input | Gate 1 input D; input voltage range -0.5 V to VDD+0.5 V. |
| 6 | NC | unconnected | Not shown in the CD4072B functional diagram; no internal connection indicated. |
| 7 | VSS | power_in | Ground / negative supply reference; all VDD voltages are referenced to VSS. |
| 8 | NC | unconnected | Not shown in the CD4072B functional diagram; no internal connection indicated. |
| 9 | E | input | Gate 2 input E; input voltage range -0.5 V to VDD+0.5 V. |
| 10 | F | input | Gate 2 input F; input voltage range -0.5 V to VDD+0.5 V. |
| 11 | G | input | Gate 2 input G; input voltage range -0.5 V to VDD+0.5 V. |
| 12 | H | input | Gate 2 input H; input voltage range -0.5 V to VDD+0.5 V. |
| 13 | K | output | Output of OR gate 2 (K = E+F+G+H); symmetrical output drive, IOL min 0.51 mA at VDD = 5 V, 25°C. |
| 14 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `CD4072BPW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4072bpw-etched.step` / `cd4072bpw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4072bpw.step` / `cd4072bpw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4072b.pdf) (34 pp, sha256 `e6108f3d67797b70`, retrieved 2026-10-07, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4072bpw-datasheet.pdf)