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CD4072BM96

Public Made by Adom

by adom

Texas Instruments Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cd4072bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cd4072bm96: viewers · Ray 2mo ago
cd4072bm96-etched.fit.json cd4072bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4072bm96-etched.glb cd4072bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
cd4072bm96-etched.step cd4072bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
cd4072bm96.glb Publish 0.1.0 · Ray 2mo ago
cd4072bm96.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4072bm96.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4072bm96.lbr Publish 0.1.0 · Ray 2mo ago
cd4072bm96.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json cd4072bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 14d ago
README.md cd4072bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4072BM96

Texas Instruments · Gates · SOIC-14

CD4072BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 J output Output of gate 1 (J = A + B + C + D). Buffered CMOS output with symmetrical source/sink drive.
2 A input Input A of gate 1 (4-input OR). High-impedance CMOS input, ESD-protected by internal diode/resistor network. Unused inputs must be tied to VDD or VSS.
3 B input Input B of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
4 C input Input C of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
5 D input Input D of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
6 NC unconnected No internal connection. Leave floating or tie to any convenient rail.
7 VSS power_in Negative supply / ground reference. Typically 0 V; all input and output voltages are referenced to VSS.
8 NC unconnected No internal connection. Leave floating or tie to any convenient rail.
9 E input Input E of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
10 F input Input F of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
11 G input Input G of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
12 H input Input H of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS.
13 K output Output of gate 2 (K = E + F + G + H). Buffered CMOS output with symmetrical source/sink drive.
14 VDD power_in Positive supply voltage. Operating range 3 V to 18 V; absolute maximum -0.5 V to +20 V referenced to VSS. Decouple to VSS at the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4072BM96
  • CD4072BM96E4
  • CD4072BM96G4
  • CD4072BM96M
  • CD4072BM96ME4
  • CD4072BM96MG4
  • CD4072BM96MT
  • CD4072BM96MTE4
  • CD4072BM96MTG4
  • CD4072BM96E
  • CD4072BM96EE4
  • CD4072BM96F
  • CD4072BM96F3A
  • CD4072BM96NSR
  • CD4072BM96NSRE4
  • CD4072BM96NSRG4
  • CD4072BM96PW
  • CD4072BM96PWR
  • CD4072BM96PWE4
  • CD4072BM96PWG4
  • CD4072BM96PWRE4
  • CD4072BM96PWRG4

CAD (KiCad official)

  • Symbol: CD4072BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4072bm96-etched.step / cd4072bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4072bm96.step / cd4072bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 81aca00a04398327, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF